A PVT-tracking metastability detector for asynchronous ADCs

Asynchronous SAR ADC with self‐timed track‐and‐hold

“…Introduction: SAR ADCs are widely used due to their medium-to-high resolution, low power consumption, and compact size [1][2][3][4]. Conventional asynchronous topology enables faster operation by the self-timed mechanisms [5][6][7][8], as shown in Figure 1a. These mechanisms comprise track-and-hold (T/H) and conversion periods [4], with the endpoint of each conversion dynamically determined for every sampling instance [5][6][7][8].…”

“…Conventional asynchronous topology enables faster operation by the self-timed mechanisms [5][6][7][8], as shown in Figure 1a. These mechanisms comprise track-and-hold (T/H) and conversion periods [4], with the endpoint of each conversion dynamically determined for every sampling instance [5][6][7][8]. Typical asynchronous architectures require a high-frequency input clock to generate a predetermined T/H period [9,10], and each clock cycle also needs a margin to account for clock jitter [11].…”