Asynchronous SAR ADC with self‐timed track‐and‐hold
Sunghyun Bae,
Sewon Lee,
Siheon Seong
et al.
Abstract:This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a … Show more
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