An energy-efficient switching scheme for a low-power successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. Taking the parasitic capacitance of the capacitor array into consideration, the average switching energy of the proposed scheme can be reduced by 97.4% compared with the conventional architecture. The proposed scheme also reduces the number of capacitors in the capacitor array by 75.5% and hence achieves area efficiency with high performance.
An energy-efficient successive approximation register (SAR) analogue-to-digital converter (ADC) switching scheme is proposed for low-power biomedical applications. By dramatically reducing energy consumption in the first three bit-cycles, the average switching energy of the proposed scheme is reduced by 98.8% compared with the conventional architecture. The number of capacitors in the capacitor array of this proposed scheme is also reduced by 75.5% over the conventional approach. Introduction: Charge redistribution successive approximation register (SAR) analogue-to-digital converters (ADCs) are very popular with biomedical electronics due to their advantage of high energy efficiency. Recently, various capacitor switching schemes have been proposed to reduce the power consumption of SAR ADCs [1-9]. Energy reductions are achieved by capacitor splitting [1], monotonic switching [2] and different tri-level switching methods [3-9]. However, the switching schemes in [1-3] still consume substantial energy, especially during the generation of the first several bits, where the relatively large capacitors need to change their connections. The schemes mentioned in [4-7, 9] improve this to some extent, but a considerable amount of energy is still consumed during the first few bits. Moreover, since the tri-level switching schemes in [3-6] start to use the sub-reference V cm , which should be equal to V ref /2, at the first bit-cycle, they are strongly dependent on the accuracy of V cm. The scheme in [7] shows that average energy is reduced by more than 98% compared with the conventional architecture, but this calculation directly accumulates the negative energy which should have been wasted, decreasing the attraction of their analysis and comparison. In this Letter, an energy-efficient capacitor switching scheme is proposed for SAR ADC. Behavioural simulations show that the proposed scheme reduces the average switching energy by 98.8% over the conventional architecture.
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