A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Abstract

This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spuriousfree dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-tonoise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step. KEYWORDSA/D converter (ADC), binary window, D/A converter (DAC), successive approximation register (SAR)

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

“…Table 1 presents the performance summary of the proposed architecture and its comparison with the other state of the art architectures [ 15 , 16 , 19 , 20 , 21 ]. It is evident that the proposed architecture exhibits a competitive performance in terms of energy efficiency and linearity.…”

“…To reduce the switching energy and improve the linearity, floating DAC switching technique is presented in [ 18 ]. In [ 19 , 20 ], a binary-window DAC switching technique is presented to decrease switching error and DAC non-linearity at the cost of excessive power consumption. To decrease the distortion introduced by threshold voltage and parasitic capacitance, a linearity enhancement switch is implemented in [ 21 ].…”

Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

“…In charge‐redistribution SAR ADCs, the power consumption of the capacitor switching in the digital‐to‐analog converter (DAC) usually is dominant 1–5,9–15 . Recently, several techniques have been presented to reduce the DAC switching energy and capacitor size 1–26 …”

“…In Zhou et al, 7 a two‐step quantization results in both switching energy and capacitor area reductions. Using a reference‐free technique to avoid the static power dissipation of the on‐chip reference generation and also a common‐mode based charge recovery switching method reduces the switching energy in Zhu et al 8 The binary‐window DAC switching scheme is proposed in Chung et al 24 to linearize the SAR ADC performance effectively by using a small sampling capacitor, and hence, with reduced area and power consumption.…”

A charge sharing–based switching scheme for SAR ADCs

“…[1][2][3] To this end, several switching schemes such as monotonic, 4 high-accuracy, 5 tri-level, 6 common-mode voltage (V CM )-based, 7 hybrid, 8 dual-capacitor, 9 energy-efficient, 10 and charge recycling-based 11,12 techniques have been recently presented to improve the accuracy and the power efficiency of the capacitive DACs. However, the capacitor arrays of the digital-to-analogue converter (DAC) blocks consume the most power in comparison with the comparator and the digital control logic.…”