A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad, Khuram; Verma, Deeksha; Khan, Danial; Ain, Qurat ul; Basim, Muhammad; Kim, Sung Jin; Rikan, Behnam Samadpoor; Pu, Young Gun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

doi:10.3390/s21072260

Cited by 10 publications

(8 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It demonstrated a 40% reduction in Kick-back noise and a 10% increase in ENOB compared to other 12-bit SAR ADC based on a conventional comparator and thus provided a very high SNDR of 68.45 dB and an ENOB of 11.07 bits. In addition, the average power consumption of the ADC test chip during the data conversion operation was only 6.6 uW, which is 296 times and 71.5 times lower than the previous work of [20] and [21], respectively.…”

Section: Analog Convolution Neural Network Kernel Using Adcmentioning

confidence: 67%

“…Using the above parameters, ADC's performance was determined and compared with other works in Table 3 to have an ENOB of 11.07 bits and SNDR of 68.45 dB. The area of the ADC test chip was 0.0046 mm 2 , which is 21.3 times and 30.4 times smaller than the previous work [20] and [21], respectively. The performance of the ADC test chip was evaluated at a sampling frequency of 17.8 Ms/s for a sinusoidal input signal frequency of 6.53 kHz.…”

Section: Analog Convolution Neural Network Kernel Using Adcmentioning

confidence: 99%

See 1 more Smart Citation

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

Lee¹,

Asghar²,

Kim³

2023

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

As deep learning techniques such as Convolutional Neural Networks (CNNs) are widely adopted, the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip (SoC). Although conventional CNN accelerators can reduce the computational time of learning and inference tasks, they tend to occupy large chip areas due to many multiply-and-accumulate (MAC) operators when implemented in complex digital circuits, incurring excessive power consumption. To overcome these drawbacks, this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter (ADC). This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips. ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory. This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register (SAR) ADC. Unlink most other SAR-ADCs with differential structure; the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption. The SAR ADC implementation also introduces a unique circuit that reduces kick-back noise to increase performance. It was implemented in a test chip using a 55 nm CMOS process. It demonstrates that the proposed ADC reduces Kick-back noise by 40% and consequently improves the ADC's resolution by about 10% while providing a near rail-to-rail dynamic range with significantly lower power consumption than conventional ADCs. The ADC test chip shows a chip size of 4600 μm 2 with a power consumption of 6.6 μW while providing an signal-to-noise-and-distortion ratio (SNDR) of 68.45 dB, corresponding to an effective number of bits (ENOB) of 11.07 bits.

show abstract

Section: Analog Convolution Neural Network Kernel Using Adcmentioning

confidence: 67%

Section: Analog Convolution Neural Network Kernel Using Adcmentioning

confidence: 99%

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

Lee¹,

Asghar²,

Kim³

2023

Computers, Materials &Amp; Continua

View full text Add to dashboard Cite

show abstract

“…A stable reference voltage is required for high-resolution ADCs. For SAR ADCs, static bias current is not required in the design of the dynamic comparator [ 6 , 7 ]; hence, the overall power consumption of SAR ADC scales with the sampling rate.…”

Section: Introductionmentioning

confidence: 99%

“…Table1summarizes the performance of the proposed SAR ADC architecture and compares it with the other state-of-the-art SAR ADC architectures. The figure of Merit (FOM) is generally used to check the overall performance of ADC, and the FOM can be evaluated as below: FOM = Power ADC min(F S , 2 × BW)2 ENOB(7) where the sampling rate is presented as F S , bandwidth of ADC is denoted as BW, and power consumed by the proposed ADC is represented as Power ADC . The proposed SAR ADC architecture achieved a FOM of 66.25 fJ/conv-step.…”

mentioning

confidence: 99%

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

Verma

Shehzad

Kim

et al. 2022

Sensors

Self Cite

View full text Add to dashboard Cite

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

show abstract

“…An analog-to-digital converter (ADC) is a key component in the processing of sensor output [ 1 , 2 , 3 ] and wireless communication [ 4 , 5 ]. Among various ADCs, successive approximation register (SAR) ADC is suitable for achieving high energy efficiency with low power consumption [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

View full text Add to dashboard Cite

Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

show abstract

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Cited by 10 publications

References 28 publications

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Contact Info

Product

Resources

About