Shifting the sampled input signal in successive approximation register analog‐to‐digital converters to reduce the digital‐to‐analog converter switching energy and area

Abstract

Summary In this paper, a switching scheme is presented to reduce the capacitive digital‐to‐analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog‐to‐digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.

A 10‐bit 1GSample/s hybrid digital‐to‐analog converter with a modified thermometer decoder in 65‐nm CMOS technology

“…The main advantages of capacitive switch topologies are design simplicity, relatively good accuracy, and low‐power consumption by proper design. The mismatch error, the needed buffer at the output, and the parasitic capacitors that severely affect the circuit performance in high resolutions are among the challenges in both topologies 1–3 …”