A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme

Yen, Chia-Wei; Tsai, Pei-Kang; Chen, Bo-Wei

doi:10.1109/tvlsi.2018.2849008

Cited by 22 publications

(13 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The breakdown of power consumption with respect of sub blocks is presented in Figure 16. Table 1 presents the performance summary of the proposed architecture and its comparison with the other state of the art architectures [15,16,[19][20][21]. It is evident that the proposed architecture exhibits a competitive performance in terms of energy efficiency and Table 1 presents the performance summary of the proposed architecture and its comparison with the other state of the art architectures [15,16,[19][20][21].…”

Section: Measurement Resultsmentioning

confidence: 98%

“…Table 1 presents the performance summary of the proposed architecture and its comparison with the other state of the art architectures [ 15 , 16 , 19 , 20 , 21 ]. It is evident that the proposed architecture exhibits a competitive performance in terms of energy efficiency and linearity.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The FFT spectrum shows that it achieves an ENOB of 10.98 bit at 4 MHz input frequency and 10.58 bit at around Nyquist input frequency with a sampling rate of 20 MS/s and an input single with a peak-to-peak voltage range of 600 mV. Table 1 presents the performance summary of the proposed architecture and its comparison with the other state of the art architectures [15,16,[19][20][21]. It is evident that the proposed architecture exhibits a competitive performance in terms of energy efficiency and Figure 15a presents the trend of SFDR and SNDR versus the applied input signal frequencies at 20 MS/s with 1 V of power supply.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…To reduce the switching energy and improve the linearity, floating DAC switching technique is presented in [18]. In [19,20], a binary-window DAC switching technique is presented to decrease switching error and DAC non-linearity at the cost of excessive power consumption. To decrease the distortion introduced by threshold voltage and parasitic capacitance, a linearity enhancement switch As a result of the breakneck advancement in wireless technologies, a number of communication standard applications including ITS transceivers require on-chip ADCs with a sampling speed of few tens of MS/s and a resolution of more than 10 bits.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

View full text Add to dashboard Cite

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

show abstract

Section: Measurement Resultsmentioning

confidence: 98%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

View full text Add to dashboard Cite

show abstract

“…[7] proposed a new circuit applied the negative DAC side to reduce the dielectric relaxation effect and improve ADC performance. Some other ADC adapts the hybrid structure to improve the sampling rate [8][9][10]. Design different switching strategies to reduce quantization error and power consumption [11].…”

Section: Introductionmentioning

confidence: 99%

Low Power SAR ADC Design with Digital Background Calibration Algorithm

Chen

Liang

et al. 2020

Symmetry

View full text Add to dashboard Cite

This paper proposed a digital background calibration algorithm with positive and negative symmetry error tolerance to remedy the capacitor mismatch for successive approximation register analog-to-digital converters (SAR ADCs). Compensate for the errors caused by capacitor mismatches and improve the ADC performance. Combination with a tri-level switching scheme based on the common-mode voltage Vcm to achieve capacitor reduction and high switching energy efficiency. The proposed calibration algorithm significantly improves capacitor mismatch without resorting to extensive computation or dedicated circuits. The active area is 0.046 mm2 in 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The post-simulation results show the effective number of bits (ENOB) improves from 8.23 bits to 11.36 bits, signal-to-noise-and distortion ratio (SNDR) improves from 51.33 dB to 70.15 dB, respectively, before and after calibration. This improves the spurious-free dynamic range (SFDR) by 24.13 dB, from 61.50 dB up to 85.63 dB. The whole ADC’s power consumption is only 0.3564 mW at sampling rate fs =2 MS/s and Nyquist input frequency, with a figure-of-merit (FOM) 67.8 fJ/conv.-step.

show abstract

An Area Effective and High Speed SAR ADC Architecture for Wireless Communication

Prathiba¹,

Santhi²

2020

Second International Conference on Computer Networks and Communication Technologies

View full text Add to dashboard Cite

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme

Cited by 22 publications

References 13 publications

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Low Power SAR ADC Design with Digital Background Calibration Algorithm

An Area Effective and High Speed SAR ADC Architecture for Wireless Communication

Contact Info

Product

Resources

About