A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS

Yen, Chia-Wei; Wu, Meng-Hsuan

doi:10.1109/tvlsi.2016.2547958

Cited by 11 publications

(4 citation statements)

References 15 publications

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“…Duality concept is very much relevant to fast and high data processing. A dual circuit of DAC implemented in Chung et al (2016) that is very much helpful for high data processing. There is still a big area for the duality circuits in SAR-ADC, such as bootstrapped switch and comparator.…”

Section: Problem Statementmentioning

confidence: 99%

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Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Faheem

Zhong

Wang

et al. 2021

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Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

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Section: Problem Statementmentioning

confidence: 99%

“…In the capacitive DAC circuit, the capacitors are the main components for its designing, which consume a significant amount of energy and power. In Chung et al (2016), the twostep decision concept is used, which is not a time-efficient solution due to its continuous conversion process.…”

Section: Digital To Analog Convertermentioning

confidence: 99%

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Faheem

Zhong

Wang

et al. 2021

View full text Add to dashboard Cite

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“…To improve the energy efficiency and resolution of SAR ADC, researches focused on digitalto-analog converter (DAC) switching scheme and comparator have been developed [4][5][6][7][8][9][10][11][12][13][14]. Many energy-efficient DAC switching schemes have been developed to reduce the switching energy during SAR conversion [4,[14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

A Time-Domain Comparator Based Skipping-Window SAR ADC

Xie¹,

Ren²,

Zhou³

et al. 2021

Computers, Materials &Amp; Continua

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This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The timedomain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.

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“…Binary capacitor arrays are usually applied as the digital-to-analog converter (DAC) parts in these structures. Nevertheless, as the resolution of these structures increases, the number of the capacitors in the capacitor DAC (CDAC) also increases, which makes the structure bulky [1,2]. In addition, the mismatch in the CDAC degrades the performance of these structures [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

et al. 2018

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This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively.

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A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS

Cited by 11 publications

References 15 publications

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

A Time-Domain Comparator Based Skipping-Window SAR ADC

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

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