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Single junction InGaP/GaAs solar cells displaying high efficiency and record high open‐circuit voltage values have been grown by metal–organic chemical vapor deposition on Ge/graded SiGe/Si substrates. Open‐circuit voltages of 980 mV under AM0 conditions have been verified to result from a single GaAs junction, with no evidence of Ge‐related sub‐cell photoresponse. AM0 efficiencies close to 16% have been measured for a large number of small‐area cells, the performance of which is limited by non‐fundamental current losses due to significant surface reflection resulting from> 10% front‐surface metal coverage and wafer handling during the growth sequence for these prototype cells. It is shown that at the material quality currently achieved for GaAs grown on Ge/SiGe/Si substrates, namely a 10 ns minority‐carrier lifetime that results from complete elimination of anti‐phase domains, and maintaining a threading dislocation density of ∼8 × 105 cm−2, 19–20% AM0 single‐junction GaAs cells are imminent. Experiments show that the high performance is not degraded for larger‐area cells, with identical open‐circuit voltages and higher short‐circuit current (due to reduced front metal coverage) values being demonstrated, indicating that large‐area scaling is possible in the near term. Comparison with a simple model indicates that the voltage output of these GaAs‐on‐Si cells follows the ideal behavior expected for lattice‐mismatched devices, demonstrating that unaccounted‐for defects and issues that have plagued other methods to epitaxially integrate III–V cells with Si are resolved by using SiGe buffers and proper GaAs nucleation methods. These early results already show the enormous and realistic potential of the virtual SiGe substrate approach for generating high‐efficiency, lightweight and strong III–V solar cells. Copyright © 2002 John Wiley & Sons, Ltd.

The minority carrier lifetime of electrons (τn) in p-type GaAs double heterostructures grown on GaAs substrates and compositionally graded Ge/Si1−xGex/Si (SiGe) substrates with varying threading dislocation densities (TDDs) were measured at room temperature using time-resolved photoluminescence. The electron lifetimes for homoepitaxial GaAs and GaAs grown on SiGe (TDD∼1×106 cm−2) with a dopant concentration of 2×1017 cm−3 were ∼21 and ∼1.5 ns, respectively. The electron lifetime measured on SiGe was substantially lower than the previously measured minority carrier hole lifetime (τp) of ∼10 ns, for n-type GaAs grown on SiGe substrates with a similar residual TDD and dopant concentration. The reduced lifetime for electrons is a consequence of their higher mobility, which yields an increased sensitivity to the presence of dislocations in GaAs grown on metamorphic buffers. The disparity in dislocation sensitivity for electron and hole recombination has significant implications for metamorphic III-V devices.

Recent experimental measurements have shown that in GaAs with elevated threading dislocation densities (TDDs) the electron lifetime is much lower than the hole lifetime [C. L. Andre, J. J. Boeckl, D. M. Wilt, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, B. M. Keyes, and S. A. Ringel, Appl. Phys. Lett. 84, 3884 (2004)]. This lower electron lifetime suggests an increase in depletion region recombination and thus in the reverse saturation current (J0 for an n+∕p diode compared with a p+∕n diode at a given TDD. To confirm this, GaAs diodes of both polarities were grown on compositionally graded Ge∕Si1−xGex∕Si (SiGe) substrates with a TDD of 1×106cm−2. It is shown that the ratio of measured J0 values is consistent with the inverse ratio of the expected lifetimes. Using a TDD-dependent lifetime in solar cell current–voltage models we found that the Voc, for a given short-circuit current, also exhibits a poorer TDD tolerance for GaAs n+∕p solar cells compared with GaAs p+∕n solar cells. Experimentally, the open-circuit voltage (Voc) for the n+∕p GaAs solar cell grown on a SiGe substrate with a TDD of ∼1×106cm−2 was ∼880mV which was significantly lower than the ∼980mV measured for a p+∕n GaAs solar cell grown on SiGe at the same TDD and was consistent with the solar cell modeling results reported in this paper. We conclude that p+∕n polarity GaAs junctions demonstrate superior dislocation tolerance than n+∕p configured GaAs junctions, which is important for optimization of lattice-mismatched III–V devices.

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