A 10Gb/s CDR with a half-rate bang-bang phase detector

Ramezani, Mehrdad; Andre, C.; Salama, T.

doi:10.1109/iscas.2003.1205927

Cited by 16 publications

(9 citation statements)

References 8 publications

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“…Effectively, this block generates 8-subsequent samples of the input data during the bit period. This is similar to the one used in the improved bang-bang phase detector in [7], [8].…”

Section: Samplermentioning

confidence: 81%

Architecture of a Fully Digital CDR for Plesiochronous Clocking Systems

Kilada

Dessouky

El-Hennawy

2007

2007 IEEE International Conference on Signal Processing and Communications

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This paper describes a design of a fully digital clock and data recovery (CDR) system with plesiochronous clocking. Besides the well known advantages of digital implementations over analog ones in terms of robustness against process and temperature variations, scalability, compactness and low cost, the system also enjoys many features. It can withstand an input data cycle-to-cycle jitter up to ±37.5% Ul. Data are obtained through digital correlation with the incoming symbol instead of ordinary sampling at the middle of the eye pattern, which improves BER. Furthermore, it needs only, at worst, three preamble bits to get into lock. It is insensitive to long runs of transition-free data patterns. The extracted data clock is not shifted as long as input data jitter is small (typically less than ±12.5%UI), thus, minimizing jitter in the extracted data clock. Besides, the extracted clock has a 50% duty cycle.Index Terms-Clock and data recovery (CDR), clock multiplication, phase locking, jitter filtering.

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“…Effectively, this block generates 8-subsequent samples of the input data during the bit period. This is similar to the one used in the improved bang-bang phase detector in [7], [8].…”

Section: Samplermentioning

confidence: 81%

Architecture of a Fully Digital CDR for Plesiochronous Clocking Systems

Kilada

Dessouky

El-Hennawy

2007

2007 IEEE International Conference on Signal Processing and Communications

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“…The program takes advantage of Eqs. (1)(2)(3)(4) to quickly determine how the state of a PLL changes. Every time step T, the program updates and outputs the state of a given PLL, and then checks to see if that PLL has locked or not.…”

Section: Bang-bang Pll Behaviourmentioning

confidence: 99%

“…performance [1][2][3]. Specifically, bang-bang PDs can run at the highest speed a process can make a flip-flop, and suffer no systematic phase offset since data is sampled as part of the phase detector's operation.…”

mentioning

confidence: 99%

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Chan

Postula

Ding³

et al. 2006

Analog Integr Circ Sig Process

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Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

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“…Clock and data recovery (CDR) with a binary phase detector possesses a number of critical advantages over those with a linear phase detector including low sensitivity to process and component variation, automatic data re-timing, a large acquisition range, and a high lock speed [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. Binary phase detectors allocate data transitions by strobing input data multiple times per data eye.…”

Section: Introductionmentioning

confidence: 99%

A new current-integrating bang-bang phase detector for clock and data recovery

Yuan

2008

2008 51st Midwest Symposium on Circuits and Systems

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This paper proposes a new current-integrating bang-bang phase detector that is insensitive to data transient disturbances. The phase detector extracts early-late phase information between the input and retimed data by integrating the input data and its complementary on two identical capacitors. In addition, it employs only one regenerative DFF for phase detection, significantly lowering hardware cost. The phase detector has been implemented in TSMC-0.18µm 1.8V CMOS technology and analyzed using Spectre-RF from Cadence Design Systems with BSIM3.3v device models. Simulation results are presented.

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A 10Gb/s CDR with a half-rate bang-bang phase detector

Cited by 16 publications

References 8 publications

Architecture of a Fully Digital CDR for Plesiochronous Clocking Systems

Architecture of a Fully Digital CDR for Plesiochronous Clocking Systems

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

A new current-integrating bang-bang phase detector for clock and data recovery

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