A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Abstract

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool

“…A simplified version of this model is successfully used in [4] to derive an expression for (2.5) PLL capture range.…”

“…[4] presents an analytic expression to predict a conservative capture range of a bang-bang PLL, but no such equations exist yet to predict locking time, and PLL jitter and tracking performance in lock. Consequently the design process for bang-bang phase locked systems is very reliant on simulation tools.…”

A new current-integrating bang-bang phase detector for clock and data recovery

“…Clock and data recovery (CDR) with a binary phase detector possesses a number of critical advantages over those with a linear phase detector including low sensitivity to process and component variation, automatic data re-timing, a large acquisition range, and a high lock speed [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. Binary phase detectors allocate data transitions by strobing input data multiple times per data eye.…”

Jitter transfer and jitter tolerance analysis of bang-bang clock and data recovery circuits

“…Third order bang-bang PLL loop Other efforts include Chan et al who analyzed the first and second order bang-bang PLL loops based on Walker models using transient analysis. In his work he discussed the cycle slipping and the far from lock regions[40,41].…”