Single junction InGaP/GaAs solar cells displaying high efficiency and record high open‐circuit voltage values have been grown by metal–organic chemical vapor deposition on Ge/graded SiGe/Si substrates. Open‐circuit voltages of 980 mV under AM0 conditions have been verified to result from a single GaAs junction, with no evidence of Ge‐related sub‐cell photoresponse. AM0 efficiencies close to 16% have been measured for a large number of small‐area cells, the performance of which is limited by non‐fundamental current losses due to significant surface reflection resulting from> 10% front‐surface metal coverage and wafer handling during the growth sequence for these prototype cells. It is shown that at the material quality currently achieved for GaAs grown on Ge/SiGe/Si substrates, namely a 10 ns minority‐carrier lifetime that results from complete elimination of anti‐phase domains, and maintaining a threading dislocation density of ∼8 × 105 cm−2, 19–20% AM0 single‐junction GaAs cells are imminent. Experiments show that the high performance is not degraded for larger‐area cells, with identical open‐circuit voltages and higher short‐circuit current (due to reduced front metal coverage) values being demonstrated, indicating that large‐area scaling is possible in the near term. Comparison with a simple model indicates that the voltage output of these GaAs‐on‐Si cells follows the ideal behavior expected for lattice‐mismatched devices, demonstrating that unaccounted‐for defects and issues that have plagued other methods to epitaxially integrate III–V cells with Si are resolved by using SiGe buffers and proper GaAs nucleation methods. These early results already show the enormous and realistic potential of the virtual SiGe substrate approach for generating high‐efficiency, lightweight and strong III–V solar cells. Copyright © 2002 John Wiley & Sons, Ltd.

GaP/Si heterostructures were grown by metal-organic chemical vapor deposition in which the formation of all heterovalent nucleation-related defects (antiphase domains, stacking faults, and microtwins) were fully and simultaneously suppressed, as observed via transmission electron microscopy (TEM). This was achieved through a combination of intentional Si(100) substrate misorientation, Si homoepitaxy prior to GaP growth, and GaP nucleation by Ga-initiated atomic layer epitaxy. Unintentional (311) Si surface faceting due to biatomic step-bunching during Si homoepitaxy was observed by atomic force microscopy and TEM and was found to also yield defect-free GaP/Si interfaces. V

SiGe-free strained Si on insulator substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed Si0.68Ge0.32 graded layers. Raman spectroscopy shows that the 49-nm thick strained Si on insulator structure maintains a 1.15% tensile strain even after SiGe layer removal. The strain in the structure is thermally stable during 1000 °C anneals for at least 3 min, while more extreme thermal treatments at 1100 °C cause slight film relaxation. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator forms an ideal platform for future generations of Si-based microelectronics.

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