Analysis of a half-rate bang-bang phase-locked-loop

Ramezani, Mehrdad; Andre, C.; Salama, T.

doi:10.1109/tcsii.2002.805020

Cited by 22 publications

(17 citation statements)

References 9 publications

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“…Two equivalent representations of the second order bangbang CDR circuits have been used by researchers [1][2][3][4]. The first representation, which was first introduced by Walker [1], is shown in Fig.…”

Section: Jitter Transfer Analysismentioning

confidence: 99%

Unifying approach for jitter transfer analysis of bang-bang CDR circuits

Gabr

Kwaśniewski

2010

2010 International Conference on Electronics and Information Engineering

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Clock and data recovery (CDR) circuits using bangbang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop filter (LF). The two-state output causes the behavior of the BBPD to be highly nonlinear and difficult to analyze. This paper provides a detailed analysis of the jitter transfer for second order bang-bang CDR circuits. Two popular representations of the second order bang-bang CDR circuits are used for our analysis. A detailed derivation of the jitter transfer expression is presented using each representation. Then a modified expression is derived, which is then verified by a phase-domain model implemented in Simulink. Simulation results show good agreement with the derived expression.

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Section: Jitter Transfer Analysismentioning

confidence: 99%

Unifying approach for jitter transfer analysis of bang-bang CDR circuits

Gabr

Kwaśniewski

2010

2010 International Conference on Electronics and Information Engineering

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“…Recent works analysing bang-bang type PLLs [3,[6][7][8][9] have focussed on jitter and tracking performance when close to lock, but fail to give any insight into behaviour given a significant frequency error. The analysis presented yields a limit for pull-in range stability.…”

mentioning

confidence: 99%

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Chan

Postula

Ding³

et al. 2006

Analog Integr Circ Sig Process

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Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

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“…Linear phase detectors avoid this problem by virtue of featuring a stable, non-quantized output in the locked state. A detailed analysis of jitter in these types of phase detectors can be found at [159]. It was experimentally verified that the amount of residual jitter in the Alexander detector used in the proposed implementation was non-trivial, and that the additional embedded PLL shown in Fig.…”

Section: Clocking Schemementioning

confidence: 86%

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

Varea¹,

Ramón²

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Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals.The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one.As a first step, a general study of DAQ architectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock iii alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards.Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the...

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Analysis of a half-rate bang-bang phase-locked-loop

Cited by 22 publications

References 9 publications

Unifying approach for jitter transfer analysis of bang-bang CDR circuits

Unifying approach for jitter transfer analysis of bang-bang CDR circuits

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

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