This paper describes a delta-sigma ( A-Z ) modulation and fractional-S frequency division technique to perform indirect digital frequency synthesis based on the use of a phaselocked loop (PLL). The use of 1 -Y modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-S division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional--Y PLL techniques. Phase Detector Loop Filter vco Spurious Frequencies Precision Analog Components Required Minimum Complexity of Digital Hardware Introduces Broad Band

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CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-m CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with 083 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption. Index Terms-CMOS oscillator, ECO, emitter coupled oscillator, linearized MOSFET model, multivibrator, phase locked loop, phase noise simulation, PLL frequency synthesizer, relaxation oscillator, ring oscillator, VCO, voltage controlled oscillator.

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This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC implementation and exhibits high potential for a gigahertz range, low-power monolithic CMOS frequency synthesizer.

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A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18µm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.