A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

Phase Lock Loop (PLL) and Delay Locked Loops (DLLs) are major analog circuits used for many different communication applications such as frequency synthesizer, radio, computer, clock generation and recovery, global positioning system etc. This paper developed a methodical approach to calculate jitter of the PLL and DLL. The methodological nature of our approach would manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the same. Finally, jitter of DLL has been reduced by proposed technique.

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“…8,2,5 This conclusion can be proved by (15). The experimental results of the methodical approach are shown in Figs.…”

Section: Jitter Due To Reference Jittermentioning

confidence: 61%

Predicting the Jitter of Pll–dll Based Frequency Synthesizers

Patel¹,

Sharma

2014

Int. J. Wavelets Multiresolut Inf. Process.

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“…PLLs, however, require a large loop filter capacitor and exhibit jitter accumulation problems. Multiplying delay-locked loops (MDLLs) [2][3][4] have been adopted for integer-ratio (×N) frequency multiplication, and shown promise as replacements for PLLs. Also, fractional-ratio frequency multiplying DLL (FFMDLL) has been introduced recently, which can provide ×N/M multiplication without producing a clock skew between the input and the output clocks [5].…”

Section: Introductionmentioning

confidence: 99%

An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

Han¹,

Lim²,

Kim

2016

JSTS:Journal of Semiconductor Technology and Science

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“…Although [5] was introduced to avoid harmonic locking, it requires a complicated error detector circuit with large on-chip capacitors and area overhead.…”

Section: Introductionmentioning

confidence: 99%

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

Park¹,

Kim²,

Kim³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

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A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

Cited by 58 publications

References 7 publications

Predicting the Jitter of Pll–dll Based Frequency Synthesizers

Predicting the Jitter of Pll–dll Based Frequency Synthesizers

An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

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