A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

Abstract

Abstract-A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

“…PLLs, however, require a large loop filter capacitor and exhibit jitter accumulation problems. Multiplying delay-locked loops (MDLLs) [2][3][4] have been adopted for integer-ratio (×N) frequency multiplication, and shown promise as replacements for PLLs. Also, fractional-ratio frequency multiplying DLL (FFMDLL) has been introduced recently, which can provide ×N/M multiplication without producing a clock skew between the input and the output clocks [5].…”