A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

Zhuang, Jingcheng; Du, Qingjin; Kwaśniewski, T.

doi:10.1109/cicc.2007.4405790

Cited by 17 publications

(15 citation statements)

References 7 publications

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“…Numerous works on ADPLL have been presented in the past [1] [2] [3][5] [6][7] [8], in which the Digitally Controlled Oscillator (DCO) is at the heart. Unlike the traditional analog VCO, the oscillator in ADPLL is digitally controlled so that some quantization error exists.…”

Section: Introductionmentioning

confidence: 99%

A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

Hsu

Huang

2009

2009 International Symposium on VLSI Design, Automation and Test

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In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase locking, we propose a three-step locking procedure. The phase can be locked quickly through a preliminary phase locking scheme and the jitter is then reduced by the proposed suppressive digital loop filter. Simulation results show the jitter performance is very close to that of free running DCO. The jitter Pk-Pk and jitter RMS is 51ps and 6.74ps respectively when the output clock of ADPLL operates at 200Mhz.

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Section: Introductionmentioning

confidence: 99%

A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

Hsu

Huang

2009

2009 International Symposium on VLSI Design, Automation and Test

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“…All digital PLL has been reported to have superior performance at lower cost [1] [2]. However its fractional-N operation induces high fractional spurs [3][4] [5] when compared to a conventional charge pump-based fraction-N PLL [6], which is still most popular architecture used in synthesizer of mobile communication, thus limiting the applications of ADPLLs in high-end products.…”

Section: Introductionmentioning

confidence: 99%

A fractional spur reduction technique for RF TDC-based all digital PLLs

Wang¹,

Chang²,

Zhan³

2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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“…ADPLL implementations also include Refs. [6], [7], [8], [10], [11], [12], [13], [14] and [25]. It should be noted that there have been reported other all-digital PLL implementations, such as Refs.…”

Section: Figmentioning

confidence: 99%

“…The published ADPLLs fall into two major architectural types: the feedback-divider-based topology [6], [7], [8], [9], as shown in Fig. 1 (a); and feedback-divider-less counter-based topology [3], [4], [5], [10], [11], [12], [13], [14], [15], [16], as shown in Fig.…”

Section: Adpll Categoriesmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS

Cited by 17 publications

References 7 publications

A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

A low-jitter all-digital phase-locked loop using a suppressive digital loop filter

A fractional spur reduction technique for RF TDC-based all digital PLLs

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

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