This paper describes a delta-sigma ( A-Z ) modulation and fractional-S frequency division technique to perform indirect digital frequency synthesis based on the use of a phaselocked loop (PLL). The use of 1 -Y modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-S division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional--Y PLL techniques. Phase Detector Loop Filter vco Spurious Frequencies Precision Analog Components Required Minimum Complexity of Digital Hardware Introduces Broad Band

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