Techniques for in-band phase noise reduction in ΔΣ synthesizers

Riley, T.A.D.; Filiol, Norm; Du, Qingqing; Kostamovaara, J.

doi:10.1109/tcsii.2003.819132

Cited by 67 publications

(32 citation statements)

References 9 publications

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“…The fractional-operation in steady state requires phase interpolators or high-order modulators to reduce fractional spurs [12], [13]. Since quantization noise of such fractional spur reduction circuits can fold into and corrupt the PLL spectrum via loop nonlinearities, more efforts are required to minimize loop nonlinearities [2], [14]- [16]. This design complexity is compounded by the fact that the negative impact of the quantization noise is hard to predict [17].…”

Section: A Feature 1-simultaneous Achievement Of Fast Locking and Dementioning

confidence: 99%

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Woo

Liu

Nam

et al. 2008

IEEE J. Solid-State Circuits

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Abstract-We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-mode during phase lock and in a wider-bandwidth, fractionalmode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-PLL and design simplicity of the integer-PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.Index Terms-Charge-pump phase-locked loops, fractionalfrequency synthesizers, integer-frequency synthesizers, phaselocked loops.

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Section: A Feature 1-simultaneous Achievement Of Fast Locking and Dementioning

confidence: 99%

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Woo

Liu

Nam

et al. 2008

IEEE J. Solid-State Circuits

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“…This will improve the linearity of the phase detector (PD), which is composed of PFD and CP. As a result, noise generated by the SDM and folded down to small frequency offsets in the nonlinear PD is reduced, as described in [31,32,33,34,35]. Second, the PD linearity will be further improved by reducing turnon and turn-off time of CP1 in the fine tuning loop.…”

Section: Measurement Resultsmentioning

confidence: 99%

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Peters

Osmany

et al. 2010

Analog Integr Circ Sig Process

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We present an integrated fractional-N lownoise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

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“…Due to the nonlinearities of the building blocks in the PLL, the highfrequency spurious tones can be brought into the signal bandwidth through intermodulation products. The inputreferred rms phase error U at the PFD can be simply represented as [7]:…”

Section: Simulation Resultsmentioning

confidence: 99%

Behavioral modeling and simulation of fractional-N frequency synthesizer

Huang

Wang

2009

Analog Integr Circ Sig Process

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A set of behavioral voltage-domain verilogA/ verilog models is proposed in the paper, based on mathematical models of building blocks and some simulation strategies. The models include nonlinear effects of building blocks and can accurately predict the dynamic or stable characteristic of the closed loop. A three-order RD fractional-N PLL based frequency synthesizer with a 1.9 GHz central output frequency is implemented with the presented way. Cadence SpectreVerilog simulation results show that the behavioral modeling can provide a great speed-up over the transistor-level simulation. Correspondingly, the phase noise, spurious tones and loop locked time can also be accurately predicted, so it is helpful to optimization design based on system-level.

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Techniques for in-band phase noise reduction in ΔΣ synthesizers

Cited by 67 publications

References 9 publications

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Behavioral modeling and simulation of fractional-N frequency synthesizer

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