Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Woo, Kyoungho; Liu, Yong; Nam, Eun Soo; Ham, Donhee

doi:10.1109/jssc.2007.914281

Cited by 82 publications

(32 citation statements)

References 16 publications

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“…Many circuit design techniques have been proposed to improve the phase noise performance [1,2,3,4]. The Q-enhancement circuit [5] was proposed to compensate for the resistive loss in the integrated inductor.…”

Section: The Proposed Vcomentioning

confidence: 99%

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

Kuo

2011

IEICE Electron. Express

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This paper presents a low phase noise frequency synthesizer for WiMAX applications. The operating frequency of the proposed design ranges from 2.2 GHz to 2.4 GHz with a 1.25 MHz spacing for the 1.25 MHz to 40 MHz channel bandwidth. The proposed VCO suppresses the phase noise effectively by adopting the Q-enhancement technique, the memory reduced tail current, and a noise filter. The high speed frequency divider is implemented by an improved TSPC Dflip-flop. The proposed design is fabricated in a TSMC 0.18 μm CMOS 1P6M process. The measured phase noise is −118 Bc/Hz at an offset of 1 MHz from the center frequency. The fabricated chip consumes 25.5 mW with a 1.5 V supply and occupies a 1.1 mm 2 die area.

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Section: The Proposed Vcomentioning

confidence: 99%

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

Kuo

2011

IEICE Electron. Express

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“…In [2,3], the bandwidth is increased by k times by means of replacing the I CP (charge-pump current) with k 2 I CP and replacing the zero-controlling resistor R z with R z /k. In [4], besides the above bandwidth switching the frequency division ratio is also altered so as to lessen the burden of the large change in I CP . The disadvantage of these methods is that the loop settles slowly in the phase-locked state because of the phase disturbance caused by the large change of both I CP value and the LPF (low pass filter) structure.…”

Section: Introductionmentioning

confidence: 99%

A fast-locking fractional-<I>N</I> frequency synthesizer using a new variable bandwidth method

et al. 2013

IEICE Electron. Express

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A fast-locking fractional-N frequency synthesizer with a fourth-order PLL is presented for a receiver of multiple positioning systems. In order to reduce the locking time a new method of only performing LPF structure transformation is proposed, which exploits the large bandwidth without changing the charge-pump current during the transient state. The bandwidth of the third-order PLL with the second-order LPF during transient state is 10 times larger than that of the fourth-order PLL in the phase-locked state. Furthermore, a pre-charging circuit and the unchanged charge-pump current can significantly accelerate the phase locking. Simulation results show that the longest locking time is less than 10 μs in seven modes of three positioning systems (GPS, Galileo and Beidou). For each mode, the inband and out-of-band phase noises are no larger than −93 dBc/Hz and −118.5 dBc/Hz, respectively, and the spurs are less than −56.4 dBc at 8.043 MHz offset frequency. Total power consumption is 15.21 mW under 1.8 V supply.

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“…1, a desired reference frequency or frequency channel step ( CH f ) is generated, dividing the reference frequency ( ref f ) by R counter. Then, after locking, a frequency of VCO is determined by 4 4 /…”

Section: ⅰ Introductionmentioning

confidence: 99%

“…Consequently, this approach often requires complex calibrations to realize such a lookup table [5]. Bandwidth switching is another useful technique for decreasing the settling time [2]～ [4]. The main idea of this approach is to widen the loop bandwidth during locking and then change the bandwidth to the desired narrow one when the loop reaches a locked state.…”

Section: ⅰ Introductionmentioning

confidence: 99%

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

Heo¹,

Oh²,

Jeong³

et al. 2011

Journal of electromagnetic engineering and science

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In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 μsec and reference spur suppression below -64 dBc. Ⅰ. IntroductionA frequency synthesizer is frequently used as a signal source, and is regarded as an essential device in communication systems. Its frequency can be synthesized using the control signals from a program in a personal computer. Various implementations for frequency synthesizers are proposed [1]. One of them is using PLL (Phase Locked Loop), which is based on frequency divider. Fig. 1 shows a typical block diagram of our frequency synthesizer using frequency dividers. In comparison to a conventional frequency synthesizer, a divider of 1/4 is internally built in a voltage controlled oscillator (VCO) IC. In Fig. 1, a desired where N is division ratio of VCO frequency. Thus, the frequency of VCO can be synthesized with a step frequency CH f by changing the value of N. The important figures of merit in this type of frequency synthesizer are lock-time and reference spur suppression, which are critically dependent on the loop filter bandwidth. As a loop bandwidth increases, lock-time is decreased but spurs increase. Conversely, when a loop bandwidth decreases, spurs are suppressed but lock-time increases.Such trade-off makes it difficult to implement the loop filter to yield both a satisfactory fast lock-time and spur suppression. However, recent communication and military applications require more stringent spectral purity of signal sources, with faster settling time.To address this trade-off between settling time and loop bandwidth, several works were introduced [2]～ [6]. One design approach is to utilize a pre-determined lookup table to adjust the output frequency immediately [5], [6]. The lookup table initially records the proper frequency-setting configurations for all channels. When the PLL is commanded to change its frequency to a certain

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Fast-Lock Hybrid PLL Combining Fractional-$N$ and Integer-$N$ Modes of Differing Bandwidths

Cited by 82 publications

References 16 publications

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

A fast-locking fractional-<I>N</I> frequency synthesizer using a new variable bandwidth method

A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

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