Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis

Abstract

This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC implementation and exhibits high potential for a gigahertz range, low-power monolithic CMOS frequency synthesizer.

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

“…The amplitude of power spectrum density of the output of absolute system is related to the SDM used in the PLL, and it varies slightly with the data width and input level of SMD. The simulation is carried out for different SMDs in some published papers [1,[11][12][13][14][15][16][17]. The width of these SDMs is set to be 16, 20, 24, 28, and 32 bits, respectively.…”

“…(13). In the fourth simulation, we change the bandwidth of the phase locked loop to 0.05 MHz, 50% of the bandwidth in the first simulation by modifying the parameters of low filter.…”

“…It is the result that we expected in Eq. (13). The figures for the last three experiments are omitted to compress the manuscript length.…”

“…Fig. 7 shows the noise transfer function of some typical SDMs proposed in literatures [1,[11][12][13][14][15][16][17]. Because the SDM proposed by Fahim in [17] has a wider low-noise region, wider loop bandwidth can be allowed to achieve faster locking and better phase noise due to SDM itself.…”

Comparative study of the MASH digital delta-sigma modulators

“…They do NOT have to be prime numbers. The hardware requirement is reduced, if the MASH DDSM utilises higher order EFMs [9]. However, it results in poorer noise performance.…”