Comparative study of the MASH digital delta-sigma modulators

Xu, Tao; Condon, Marissa

doi:10.1109/rme.2009.5201293

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“…However, it produces too many fractional spurs [2]. Digital delta-sigma modulators (DDSM) [3] [4] are used to solve this problem. PLLs with DDSM are termed Delta-Sigma Fractional-N PLLs [5].…”

Section: Introductionmentioning

confidence: 99%

A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

Zhou

Shen

et al. 2011

2011 20th European Conference on Circuit Theory and Design (ECCTD)

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Abstract-A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL).

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Section: Introductionmentioning

confidence: 99%