Jitter analysis of a PLL-based CDR with a bang-bang phase detector

Ramezani, Mehrdad; Andre, C.; Salama, T.

doi:10.1109/mwscas.2002.1187056

Cited by 14 publications

(10 citation statements)

References 5 publications

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“…Each stage of the charge pump consists of two transistors acting as enables (except for the first stage), two transistors acting as switches, and two transistors acting as current sources. The current sources are sized in order to satisfy (9). The enables are controlled by the values in the dynamic gain control shift register.…”

Section: Circuit Implementation and Spice Simulation Resultsmentioning

confidence: 99%

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A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Chan

Postula

Ding³

et al. 2006

Analog Integr Circ Sig Process

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Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

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Section: Circuit Implementation and Spice Simulation Resultsmentioning

confidence: 99%

“…Recent works analysing bang-bang type PLLs [3,[6][7][8][9] have focussed on jitter and tracking performance when close to lock, but fail to give any insight into behaviour given a significant frequency error. The analysis presented yields a limit for pull-in range stability.…”

mentioning

confidence: 99%

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Chan

Postula

Ding³

et al. 2006

Analog Integr Circ Sig Process

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“…Although it has been done in other papers [4], [5], we include an analysis of a bang-bang phase detector both for completeness and to perform the analysis in the terminology that we will be using throughout the paper.…”

Section: Linearizing the Bang-bang Phase Detectormentioning

confidence: 99%

“…There have been many excellent papers on the design and analysis of this type of CDR system [1]- [5]. A linearized model is shown in Fig.…”

Section: Linearized Small-signal Modelmentioning

confidence: 99%

A digital clock and data recovery architecture for multi-gigabit/s binary links

Sonntag

Stonick

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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Abstract-In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered.Index Terms-Clock and data recovery (CDR), clock recovery, digital phase-locked loop (DPLL), jitter.

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“…Under these conditions the amount of charge added (7) In spite of the unequal UP and DOWN pulsewidths the clock and data signals are synchronized and we require the charge added by the UP pulse to be equal to the charge subtracted by the DOWN pulse. This is described as (8) Equation (7) is substituted into (8) in order to get (9) Rearranging (9) leads to a relationship between the charge pump currents, and , which make it possible for the charge pump to compensate for (10) Fig. 8 shows the normalized UP and DOWN charge pump currents resulting from (10) which will compensate for a given range of static phase offsets.…”

Section: Correction Ofmentioning

confidence: 99%

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

Rennie

Sachdev

2008

IEEE Trans. Circuits Syst. I

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This paper presents a 5-Gb/s clock and data recovery (CDR) circuit which implements a calibration circuit to correct static phase offsets in a linear phase detector. Static phase offsets directly reduce the performance of CDR circuits as the incoming data is not sampled at the center of the eye. Process nonidealities can cause static phase offsets in linear phase detectors by adversely affecting the circuits in a way which is difficult to design for, making calibration an attractive solution. Both the calibration algorithm and test chip implementation are described and measured results are presented. The CDR circuit was fabricated in a 0.18-m, six metal layer standard CMOS process. With a pseudorandom bit sequence of 2 7 1 calibration improved the measured bit error rate from 4 6 10 2 to less than 10 13 .

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Jitter analysis of a PLL-based CDR with a bang-bang phase detector

Cited by 14 publications

References 5 publications

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

A digital clock and data recovery architecture for multi-gigabit/s binary links

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

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