A digital clock and data recovery architecture for multi-gigabit/s binary links

Abstract

Abstract-In this tutorial paper, we present a general architecture for digital clock and data recovery (CDR) for high-speed binary links. The architecture is based on replacing the analog loop filter and voltage-controlled oscillator (VCO) in a typical analog phase-locked loop (PLL)-based CDR with digital components. We provide a linearized analysis of the bang-bang phase detector and CDR loop including the effects of decimation and self-noise. Additionally, we provide measured results from an implementation of the digital CDR system which are directly comparable to the linearized analysis, plus measurements of the limit cycle behavior which arises in these loops when incoming jitter is small. Finally, the relative advantages of analog and digital implementations of the CDR for high-speed binary links is considered.Index Terms-Clock and data recovery (CDR), clock recovery, digital phase-locked loop (DPLL), jitter.

Investigation of First-Order Digital Bang-Bang Phase-Locked Loops with Reference Clock Jitter

“…Assuming p(u) to be Gaussian (i.e., neglecting the loop dynamics), two expressions for K bpd reported in the literature are K bpd = 1/( √ 2πσ) for σ 1 [10] and K bpd = 2/( √ 2πσ) for σ 1 [6]. By modeling the loop dynamics using a Markov chain, the more general (approximate) expression…”

“…Note that for simplicity we assumed a uniform steady-state timing jitter PDF for small σ even if m = 0; this is only an approximation because as σ tends to zero, the limit cycle for the jitter-free case mentioned in Sec. II will persist (see [10]). …”

SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA

“…Nowadays digital clocks are also present on the rear view mirrors of the vehicles [5]. A general architecture for digital clock for high-speed binary links had also been discussed [6].A paper presents a prototype of a 6-digit digital clock displaying time on a four-digit seven-segment LED module using FPGA (field programmable gate array) [7].Our design of digital clock has been implemented on Xilinx ISE Design Suite 14.2 using different SSTL IOstandards. Comparison between different SSTL IOStandard has been done to achieve minimum IO power.…”

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications

“…An oversampling architecture [5] significantly reduced lock acquisition time using multi-phase blind oversampling. But the latency in the CDR was increased, compared with other CDR architectures [1,2,3,4] due to a wide examining window for its threshold decision technique. This paper proposes a fully digital CDR with a fast frequency-offset acquisition technique.…”

“…Some previous digital CDR architectures [1,2,3] have realized fast response recovery with a moderate frequency-offset tracking range, and another digital CDR architecture [4] has provided the advantage of an offset-free tracking ability. However, these designs have the disadvantage of a long lock-acquisition time due to slow accumulation of the integral path.…”