Abstract

In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T, package used is FBG676 and it is working on-3 speed grade. The wrist band will take the blood pressure as input and will tell about the state of the person wearing it. The design supports Internet of things service that's why IP addresses are involved. This wrist band design is very helpful in biomedical areas. Research is in progress in this field. In this paper frequency is varied to obtain power consumption of Wrist Watch. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. Main emphasis has been done on MOBILE_DDR, LVTTL, HSUL_12, HSTL_I, LVCMOS33 and SSTL15 IO Standards. To design an energy efficient device we are using capacitance scaling and the capacitance is scaled down from 100pF to 20pF. During capacitance scaling, we observe that there is no change in clock power, logic power and signal power. Thermal Aware design is current research area. Analysis has been at two temperatures that is at 25 degree Celsius and at 50 degree Celsius. At the end we can conclude that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF at both temperatures at 25 degree Celsius and 50 degree Celsius.

In this research paper, we have designed an energy efficient FIR Filter that is very much useful in digital signal processing (DSP). FIR is a finite impulse response (FIR

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as "ParavartyaYojayet". Para-vartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cumbersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have designed a Vedic divider to solve long divisions in seconds. Our design consists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathematics to solve DSP operations using Urdhava-Triyagbhayam multiplication sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capacitance maximum power is consumed at 100pF and minimum power is consumed at 20pF.Step 3: We minus divisor 12 from 10 and get -2. Multiply this -2 by first digit of 25 i.e.2 and we finally get -4 and add -4 to 25 and get 21 as quotient as shown in Figure 6. Fig. 7. RTL Schematic of Parvartya Yojayet: Part IIStep 4: Take Mod of 21 and 10 and multiply 1 (i.e.21%10) with -2 and add final result -2 in remainder 4 (in step 1) and final remainder is 2 as shown in Figure 7.

Railway safety is a crucial aspect of rail operation across the globe. In our country, there are no strong steps are taken against the unmanned level crossings and due to this accidents are increasing day by day. There is a huge increase in number of accidents as compared to last decade. India's railway system is the biggest railway network all over the Asia. And this huge network cannot be handled manually. To manage each and every railway crossing manually is not possible. Our paper basically deals with a prototype model of automatic railway barricades and discussed its working and construction. To avoid these accidents and to save road users time we have designed it. In this research work, we have placed two sensors near to the gate and these sensors will detect the arrival of the train and road users will be informed using traffic lights about the status of the train. This whole operation is automatic there is no need of human powers and is less risky and less time consuming. This automatically operatable railway barricades has increased safety of users. There are many countries in which this automatic gate control system has been implemented. In Japan, it is labeled as Automatic Train Control (ATC). Other countries with successful implementations of this system are South Korea,United Kingdom,United States, Africa etc.