A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

Rennie, D.; Sachdev, Manoj

doi:10.1109/tcsi.2008.916400

Cited by 18 publications

(9 citation statements)

References 12 publications

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“…The requirement of the SPD circuit is that its own SP should be much smaller than that of the linear PD. It is known that bang-bang phase detectors are in general insensitive to delay mismatches and can be used as a strobe point detector to calibrate the SP in a linear PD [24]. In the proposed architecture, a simple binary PD is implemented as an SPD shown in Fig.…”

Section: Phase Detector and Strobe Point Detectormentioning

confidence: 99%

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

Huang

Cao

Green

2015

IEEE J. Solid-State Circuits

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An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 m CMOS is presented. By realizing an asymmetric phase detector transfer curve, the linear CDR's "single-sided" capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the need for the reference clock and the separate frequency detector in conventional dual-loop CDRs. Robust frequency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitter tolerance performance. The measurement results show that with a 10.3 Gb/s 2 -1 PRBS input, the random jitter at the output data is 0.336 ps , and the out-ofband jitter tolerance is 0.34 UI -.Index Terms-Analog, clock-and-data recovery (CDR), CMOS, jitter tolerance, linear phase detector, receiver, referenceless, wideband data communication. 0018-9200

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Section: Phase Detector and Strobe Point Detectormentioning

confidence: 99%

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

Huang

Cao

Green

2015

IEEE J. Solid-State Circuits

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“…6. A performance summary and comparison with prior references [2], [3] is given in Table 1. The proposed CDR achieves better power efficiency than the prior arts.…”

Section: B V/i Convertermentioning

confidence: 99%

A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS

Kang

2013

2013 International SoC Design Conference (ISOCC)

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A low-power clock and data recovery(CDR) circuit with a phase detector(PD) using dynamic current-mode logic latches and a novel V/I converter is described. The proposed latch draws a current during half of the clock cycle and the proposed V/I converter includes the XOR function by itself. The half-rate CDR circuit is simulated using 5-Gb/s with 0.18-um CMOS technology, and the circuit consumes only 11.4mW from a 1.8-V supply. Keywords-Clock and Data Recovery(CDR), half-rate linear phase detector(PD)

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“…To minimize the difference in the delays, the conventional MCML XOR gate is replaced by a symmetrical MCML XOR gate shown in Fig. 5(d) [20], [21].…”

Section: A Proposed Pd Architecture and Circuit Implementationmentioning

confidence: 99%

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

Tan

Yeo

Boon

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18-CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.Index Terms-Charge Pump, Clock and Data Recovery (CDR), dual-loop, lock detector, Phase Detector (PD), quarter-rate architecture, 5-Gb/s.

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A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

Cited by 18 publications

References 12 publications

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

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A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

Cited by 18 publications

References 12 publications

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

A 5-Gb/s 11.4mW half-rate CDR in 0.18&#x03BC;m CMOS

A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector

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A 5-Gb/s 11.4mW half-rate CDR in 0.18μm CMOS