In this article, a fuzzy logic controller (FLC) tuned DC-link controller is presented. This controller is utilized to enhance the power quality characteristic of grid-integrated PV systems with power backup in comparison to the PI controller, without any filter at PCC (point of common coupling). The primary purpose of these controllers is to maintain power to the DC / AC sides by maintaining the DC-link voltage under transient conditions. The proposed system is tested with a non-linear load; hence, the proposed system requires power quality enhancements on PCC. By using both controller power flow control, reactive power compensation and harmonic mitigation is done on PCC, after that grid current becomes sinusoidal. For the power quality improvement, no filter/shunt active power filter (SAPF) is connected to PCC, only proposed inverter current controller improves the power quality at PCC by using these controllers. Using the MPPT (maximum power point tracking) Controller, the maximum power extraction feature is also included in this paper to extract maximum power from the PV module under varying atmospheric circumstances. The power backup unit is also connected with this system, power backup unit includes a battery controller which works as a boost and buck converter according to system requirements, along with a battery. On the MATLAB/Simulink platform, the control scheme and functioning of both controllers are tested, and the results are validated as satisfactory. According to IEEE 519, the grid current THD is below 5% when the suggested control system is implemented.
Application development environments for Reconfigurable Computing are the topic of many research and development projects yet few comprehensive debugging tools have been provided. In this paper we describe a debugging environment for use with FPGA accelerated applications which supports co-validation and co-testing of the software and hardware portions of the application. Our Co-debugging environment supports in-situ debugging utilizing the readback capabilities of FPGA chips for fast recreation and isolation of a fault. We show that this environment has the potential to reduce application debug times from hours to just a few minutes.
Figure 1. Reconfigurable Computing Application Model
Abstract--This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watchpoint conditions and thus, is very fast. In this paper the area overhead resulting from addition of a scan-chain based watchpoint logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.
Abstract--This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watchpoint conditions and thus, is very fast. In this paper the area overhead resulting from addition of a scan-chain based watchpoint logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.
Controllers implemented as Finite-State Machines (FSMs) occupy a major portion of FPGA designs. These FSMs can be implemented on Synchronous Embedded Memory Blocks (SEMBs) in current FPGAs. This approach, in addition to reducing considerable amount of power, also has several implementation benefits. In this research, we propose to further minimize the power consumed by the FSMs that are mapped to the SEMBs. We present an algorithm that maps the FSM outputs across the SEMBs based on its transition probabilities and thereby maximizes the dormancy of the SEMBs. For a given FSM as a state transition table, the algorithm determines for each transition in the table, the combination of inputs, outputs and state bits which contribute to the dormant transitions of the SEMB. Further, we develop a flow to determine the net power saved by this approach by computing the power consumed in the enable control logic and report the power savings for a variety of microprocessor models and MCNC benchmark circuits. Experimental results show a reduction of 8% to 21% in power compared to the SEMB based FSM technique and that it consumes 30% to 74% less dynamic power compared to the traditional LUT/FF implementation.
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