Enhanced Reliability of Finite-State Machines in FPGA Through Efficient Fault Detection and Correction

Tiwari, Anurag; Tomko, Karen

doi:10.1109/tr.2005.853438

Cited by 48 publications

(8 citation statements)

References 11 publications

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“…FPGA is also a programmability device, like programmable ROMs, and its programming techniques include antifuse-based device (Programmed Once) and static-memory-based device (Reprogrammed an Unlimited Number of Times). A typical FPGA consists of configurable logic blocks (CLB), input/output blocks (IOB), and programmable interconnects [4][5][6][7][8][9]. Each CLB can design the logical functions and latching data with combinational logic and sequential logic (AND, OR, Flipflops, and Registers).…”

Section: Fpga Development Environmentmentioning

confidence: 99%

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FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

Lin¹,

Lin²

2012

JBiSE

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This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.

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Section: Fpga Development Environmentmentioning

confidence: 99%

“…It has been applied for digital filters design [4,5], signal analysis and classification [6,7], fault detection [8], and Fuzzy logic controller [9]. For signal analysis, transform methods have been used to extract features in the transform domain, such as fast Fourier transform (FFT) and wavelet transform (WT).…”

Section: Introductionmentioning

confidence: 99%

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

Lin¹,

Lin²

2012

JBiSE

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“…Based on SRAM, FPGA tends to be damaged by space radiation, so OBC reliability design aims at FPGA mainly [14]. In the space, the electronic device is threatened by two kinds of effort: Single Event Effect (SEE) [15] and Total Ionizing Dose (TID) effect.…”

Section: ) Function Reconfiguration ： Function Reconfigurationmentioning

confidence: 99%

Run-time control design of micro-satellite OBC based on reconfigurable architecture

Zhao

Shi-jie³

et al. 2009

2009 4th IEEE Conference on Industrial Electronics and Applications

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To address the issues of On-Board Computer (OBC) design by traditional method for micro-satellite, an advanced OBC based on reconfigurable architecture was presented, and its run-time control scheduling was designed. This reconfigurable OBC could implement supervision which ensured the running status, function reconfiguration which switched its current control modes, restoring reconfiguration through searching and shielding the problem region, and software/hardware upgrading reconfiguration which could accomplish in orbit. Semi-physical simulation platform composed with OBC prototype board, DSpace simulator and laboratory terminal was established, then the performance and run-time control scheduling of this OBC was proved in the platform.

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“…This approach is very effective; however it has an extremely high cost in terms of area consumption, since the original circuits must be replicated 3 times. Hence another interesting alternative is a technique known as "scrubbing", which consists on reconfiguring the whole circuit periodically [4]. Nevertheless, this solution generates some performance overhead since the reconfiguration process takes in the order of milliseconds to be completed.…”

Section: Introductionmentioning

confidence: 99%

A study of the robustness against SEUs of digital circuits implemented with FPGA DSPs

Serrano

Clemente

Mecha

2013

2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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Abstract-In this paper we present an experimental validation of the reliability increase of digital circuits implemented in Xilinx TM FPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.

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Enhanced Reliability of Finite-State Machines in FPGA Through Efficient Fault Detection and Correction

Cited by 48 publications

References 11 publications

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

Run-time control design of micro-satellite OBC based on reconfigurable architecture

A study of the robustness against SEUs of digital circuits implemented with FPGA DSPs

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