Saving power by mapping finite-state machines into embedded memory blocks in FPGAs

Tiwari, Anurag; Tomko, Karen

doi:10.1109/date.2004.1269007

Cited by 48 publications

(51 citation statements)

References 5 publications

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“…It results in a savings of 26% power compared to LUT implementation of control logic for Finite State Machines. [21]. Bispo et al [22] touch upon a VHDL generation scheme of NFAs from SNORT ruleset.…”

Section: Related Workmentioning

confidence: 99%

Compiling PCRE to FPGA for accelerating SNORT IDS

Mitra

Najjar

Bhuyan

2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

135

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Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE Engine for regular expression matching on the payload. The software based PCRE Engine utilizes an NFA engine based on certain opcodes which are determined by the regular expression operators in a rule. Each rule in the SNORT ruleset is translated by PCRE compiler into an unique regular expression engine. Since the software based PCRE engine can match the payload with a single regular expression at a time, and needs to do so for multiple rules in the ruleset, the throughput of the SNORT IDS system dwindles as each packet is processed through a multitude of regular expressions.In this paper we detail our implementation of hardware based regular expression engines for the SNORT IDS by transforming the PCRE opcodes generated by the PCRE compiler from SNORT regular expression rules. Our compiler generates VHDL code corresponding to the opcodes generated for the SNORT regular expression rules. We have tuned our hardware implementation to utilize an NFA based regular expression engine, using greedy quantifiers, in much the same way as the software based PCRE engine. Our system implements a regular expression only once for each new rule in the SNORT ruleset, thus resulting in a fast system that scales well with new updates. We implement two hundred PCRE engines based on a plethora of SNORT IDS rules, and use a Virtex-4 LX200 FPGA, on the SGI RASC RC 100 Blade connected to the SGI ALTIX 4700 supercomputing system as a testbed. We obtain an interface throughput of (12.9 GBits/s) and also a maximum speedup of 353X over software based PCRE execution.

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Section: Related Workmentioning

confidence: 99%

Compiling PCRE to FPGA for accelerating SNORT IDS

Mitra

Najjar

Bhuyan

2007

Proceedings of the 3rd ACM/IEEE Symposium on Architecture for Networking and Communications Systems

135

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“…The maximum frequency at which a ROM-based FSM operate is independent of the complexity of the circuit. This method is also proved to save power [15]. For our HIGHT and Present architectures, the control signals are generated by a counter and some additional logic.…”

Section: Control Logicmentioning

confidence: 99%

Lightweight Cryptography for FPGAs

Yalla

Kaps

2009

2009 International Conference on Reconfigurable Computing and FPGAs

101

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Abstract-The advent of new low-power Field Programmable Gate Arrays (FPGA) for battery powered devices opens a host of new applications to FPGAs. In order to provide security on resource constrained devices lightweight cryptographic algorithms have been developed. However, there has not been much research on porting these algorithms to FPGAs. In this paper we propose lightweight cryptography for FPGAs by introducing block cipher independent optimization techniques for Xilinx Spartan3 FPGAs and applying them to the lightweight cryptographic algorithms HIGHT and Present. Our implementations are the first reported of these block ciphers on FPGAs. Furthermore, they are the smallest block cipher implementations on FPGAs using only 117 and 91 slices respectively, which makes them comparable in size to stream cipher implementations. Both are less than half the size of the AES implementation by Chodowiec and Gaj without using block RAMs. Present's throughput over area ratio of 240 Kbps/slice is similar to that of AES, however, HIGHT outperforms them by far with 720 Kbps/slice.

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“…A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs. So, it is a particular conceptualization of a particular sequential circuit which can be used for many other things beyond logic design and computer architecture [27,33,35,39,40].…”

Section: State Machinementioning

confidence: 99%

“…In general, for describing a state machine in VHDL, an enumeration type for the states can be declared, and process statements can be utilized for the state registers and the next-state logics. Other way uses three different processes: one to decode next state, one to assign current state and one for the output signals [27,33,35,39,40]. In order to be more readable and easier to debug, this thesis introduces synchronization-evolution-action approach as the way of describing as state machine in VHDL.…”

mentioning

confidence: 99%