Lightweight Cryptography for FPGAs

Yalla, Panasayya; Kaps, Jens-Peter

doi:10.1109/reconfig.2009.54

Cited by 101 publications

(31 citation statements)

References 20 publications

(27 reference statements)

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“…As can be seen from the table, our work seems to require much less area than most ciphers [40,27,21,10,28] while having a higher throughput than AES [28] implementations and also yields a better throughput per area ratio (Eff.) compared to most ciphers [27,28].…”

Section: Serialized Using Srl16smentioning

confidence: 93%

A Very Compact FPGA Implementation of LED and PHOTON

Anandakumar

Peyrin

Pöschmann

2014

Progress in Cryptology -- INDOCRYPT 2014

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Abstract. LED and PHOTON are new ultra-lightweight cryptographic algorithms aiming at resourceconstrained devices. In this article, we describe three different hardware architectures of the LED and PHOTON family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture we propose a round-based implementation while the second is a fully serialized architecture performing operations on a single cell per clock cycle. Then, we propose a novel architecture that is designed with a focus on utilizing commonly available building blocks (SRL16). This new architecture, organized in a complex scheduling of the operations, seems very well suited for recent designs that use serial matrices. We implemented both the lightweight block cipher LED and the lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix-7 (high-end) devices and our new proposed architecture provides very competitive area-throughput trade-offs. In comparison with other recent lightweight block ciphers, the implementation results of LED show a significant improvement of hardware efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash function.

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Section: Serialized Using Srl16smentioning

confidence: 93%

A Very Compact FPGA Implementation of LED and PHOTON

Anandakumar

Peyrin

Pöschmann

2014

Progress in Cryptology -- INDOCRYPT 2014

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“…As a result, there has been very few works done on the design and implementation of lightweight ciphers on FPGAs. The two most recent and promising research works are presented in [10] and [11]. The first one is mainly a comparison of the PRESENT cipher against HIGHT on FPGAs.…”

Section: Previous Workmentioning

confidence: 99%

“…The PRESENT block cipher, whose suitability for compact implementation on ASICs has been demonstrated several times can also be used on FPGAs. Until now, register based implementations of PRESENT on FPGAs have been reported [10], [11]. However, none of them have made use of the already existing block RAMs on FPGAs.…”

Section: Introductionmentioning

confidence: 99%

RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

Yalcin

2011

2011 International Conference on Reconfigurable Computing and FPGAs

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Abstract-In this paper, two different FPGA implementations of the lightweight cipher PRESENT are proposed. The main design strategy for both designs is the utilization of existing RAM blocks in FPGAs for the storage of internal states, thereby reducing the slice count. In the first design, S-boxes are realized within the slices, while in the second design they are also integrated into the same RAM block used for state storage. Both designs are well suited for lightweight applications, which are implemented on low-cost FPGA/CPLD devices. Besides low-area, a reasonable throughput is also obtained even though it is not the first concern. In addition to a single block RAM, the two designs occupy only 83 and 85 slices and produce a throughput of 6.03 and 5.13 Kbps at 100 KHz system clock on a Xilinx Spartan XC3S50 device, respectively.

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“…Embedded processors and reconfigurable devices are the prime choices for the implementation of security on hardware platforms (Wang et al, 2007;Yalla and Kaps, 2009;Rajagopalan et al, 2014a-c). Limitations on memory in embedded processors invite the special kind on crypto algorithm called Light Weight Cryptography (LWC) (Eisenbarth et al, 2007(Eisenbarth et al, , 2012.…”

Section: Introductionmentioning

confidence: 99%

Light Weight Steganography on RISC Platform-Implementation and Analysis

Janakirama¹,

Thenmozhi²,

Rayappan³

et al. 2015

Asian J. of Scientific Research

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The emergence of modern digitization has resulted in versatility to eradicate the divergence among the forms of information travel flanked by the users. This paper presents a pliable approach for the erratic block size selection in an impulsive mode to boost the level of sophistication in stego algorithm. An ingrained formula for key exchange, suggested in the algorithm combines the benefit of cryptography adjoining with steganography. In contrast to the usual implementations using generic software and personal computers, the suggested software development has been intense on an embedded device LPC 2378 with the RISC architecture that includes extensive support for networking through on-chip modules supporting ethernet and CAN protocols. The focal plan of this work includes elimination of key exchange for data encryption and improving the security to a massive level without compromising the image quality and embedding capacity. This endeavor shows the aptness of embedded hardware for stego implementations using an image carrier that makes soaring demand on memory; the extremely inhibited resource of embedded devices. The efficiency of the algorithm in maintaining image quality has been measured using the metrics MSE and PSNR. The enhancement in performance of embedded software, in terms of speed and code size have been analyzed under sophisticated compiler tools from KEIL MDK and IAREW.

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Lightweight Cryptography for FPGAs

Cited by 101 publications

References 20 publications

A Very Compact FPGA Implementation of LED and PHOTON

A Very Compact FPGA Implementation of LED and PHOTON

RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

Light Weight Steganography on RISC Platform-Implementation and Analysis

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