Light Weight Steganography on RISC Platform-Implementation and Analysis

Abstract

The emergence of modern digitization has resulted in versatility to eradicate the divergence among the forms of information travel flanked by the users. This paper presents a pliable approach for the erratic block size selection in an impulsive mode to boost the level of sophistication in stego algorithm. An ingrained formula for key exchange, suggested in the algorithm combines the benefit of cryptography adjoining with steganography. In contrast to the usual implementations using generic software and personal computers, the suggested software development has been intense on an embedded device LPC 2378 with the RISC architecture that includes extensive support for networking through on-chip modules supporting ethernet and CAN protocols. The focal plan of this work includes elimination of key exchange for data encryption and improving the security to a massive level without compromising the image quality and embedding capacity. This endeavor shows the aptness of embedded hardware for stego implementations using an image carrier that makes soaring demand on memory; the extremely inhibited resource of embedded devices. The efficiency of the algorithm in maintaining image quality has been measured using the metrics MSE and PSNR. The enhancement in performance of embedded software, in terms of speed and code size have been analyzed under sophisticated compiler tools from KEIL MDK and IAREW.