RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

Yalcin, Tolga

doi:10.1109/reconfig.2011.74

Cited by 36 publications

(22 citation statements)

References 14 publications

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“…While the first implementation uses slices for S-boxes, the second one integrates the S-boxes into the block RAM as well. This way, we provide two alternative platforms for future side channel attack (SCA) resistant implementations [6]. Willem Vereecken et.al proposed.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of Low Power Thermal Aware Atm

Dwivedi¹

2019

GJECS

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In this Paper, we have designed a Automated Teller Machine (ATM) which is electromechanical machine works in different temperature. We analysed the Static Power at discrete temperature that is thermal scaling of ATM at XILNIX 14.1 ISE Design Suit. In this paper we have used two FGPA family one is Spartan which is Spartan 6 and another is Virtex which is Virtex 4. We have distinguished on chip power by varying the Ambient temperature from 50°C to 5°C and we observed when we lowered the temperature of both FGPA families automatically the leakage power lowered that determine our ATM are worked in any temperature without disturbing its functionality.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of Low Power Thermal Aware Atm

Dwivedi¹

2019

GJECS

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“…Kavun et al [5] proposed a RAM-based FPGA implementation of PRESENT. The authors explained that the memory is used in a ping-pong fashion to store the partially encrypted data instead of using registers.…”

Section: Related Workmentioning

confidence: 99%

Compact FPGA implementation of PRESENT with Boolean S-Box

Tay

Wong

et al. 2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

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Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.

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“…For the BRAM-based implementation of PRESENT, we refer to [26] presented at ReConfig 2011. The design makes use of the existing BRAMs on the FPGA for the internal state storage, which has an impact on the reduction of the slice count.…”

Section: Ghash64(h a C) = (((X M+n ⊕ L(a)) · H ⊕ L(c)) · Hmentioning

confidence: 99%

“…The design makes use of the existing BRAMs on the FPGA for the internal state storage, which has an impact on the reduction of the slice count. In [26], only the design for PRESENT-128 is presented. For our work, we also implement PRESENT-80 -the difference of this design is in the last phase of the operation flow (key schedule).…”

Section: Ghash64(h a C) = (((X M+n ⊕ L(a)) · H ⊕ L(c)) · Hmentioning

confidence: 99%

IPSecco: A lightweight and reconfigurable IPSec core

Driessen

Güneysu

Mischke

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Abstract-In this paper we propose a reconfigurable lightweight Internet Protocol Security (IPSec) hardware core. Our architecture supports the main IPSec protocols; namely Authentication Header (AH), Encapsulating Security Payload (ESP), and Internet Key Exchange (IKE). In this work, the cryptographic algorithms and their modes of operation, which are at the heart of the IPSec protocols, are implemented in hardware. Instead of re-implementing common IPSec configurations, which are deemed "too heavy" for pervasive devices, we evaluate efficient implementations of standardized and/or well-known lightweight and hardware-friendly algorithms. In particular, we examine different versions of PRESENT, GRØSTL, PHOTON, and a very compact ECC core. As a consequence, we present IPSECCO, a core with adequate security and only moderate resource requirements, making it suitable for lightweight devices. We selected the Xilinx Spartan family of Field Programmable Gate Arrays (FPGA) as target platform due its low-power footprint and reduced costs compared to other FPGAs. Our results show that it is possible to realize a high performance IPSec core even on members of the Spartan-3 family.

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RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

Cited by 36 publications

References 14 publications

Design and Implementation of Low Power Thermal Aware Atm

Design and Implementation of Low Power Thermal Aware Atm

Compact FPGA implementation of PRESENT with Boolean S-Box

IPSecco: A lightweight and reconfigurable IPSec core

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