Hardware/software co-debugging for reconfigurable computing

Abstract

Application development environments for Reconfigurable Computing are the topic of many research and development projects yet few comprehensive debugging tools have been provided. In this paper we describe a debugging environment for use with FPGA accelerated applications which supports co-validation and co-testing of the software and hardware portions of the application. Our Co-debugging environment supports in-situ debugging utilizing the readback capabilities of FPGA chips for fast recreation and isolation of a fault. We show that this environment has the potential to reduce application debug times from hours to just a few minutes. Figure 1. Reconfigurable Computing Application Model

System‐on‐a‐chip design platform with microcomputer co‐debugging interface

“…This is not simply for debugging the microcomputer software, but is the essential function for hardware and software co-debugging that executes software on the microcomputer installed in the SoC and is able to properly control other built-in hardware functions such as the IP or peripheral I/O [6].…”

The software-hardware co-debug environment with emulator

“…The processor itself and other custom logic should be verified in the debug process. The snapshot technology is used in [8] and [9] to get the full information of the hardware at the appointed time. In [8], the read back technology is used to get the whole information of the hardware.…”

“…The snapshot technology is used in [8] and [9] to get the full information of the hardware at the appointed time. In [8], the read back technology is used to get the whole information of the hardware. It is very slow to read out the configuration bit stream from the FPGA, for the bit stream is large and the bandwidth of the JTAG is low.…”