Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs

Abstract

Abstract--This paper describes a structured and area efficient approach for in-situ debugging of application for FPGA based reconfigurable systems. A scan chain is inserted into the hardware design running on the FPGA, which helps in debugging and verification by providing watch-point capability. The scan chain technique proposed is easy to use and has very low overhead. The scan-chain based implementation capitalizes on the capability of newer FPGAs to connect several LUTs serially and configure them as shift registers. The hardware debugging procedure proposed using the shift register LUTs does not require any recompilation of the design to change the watchpoint conditions and thus, is very fast. In this paper the area overhead resulting from addition of a scan-chain based watchpoint logic is discussed and is compared with other proposed debugging techniques. We observed that this technique has an average area overhead of 46% for the ITC benchmark circuits with varying widths of watch-point signals.

gNOSIS: A Board-Level Debugging and Verification Tool

“…Overhead data for Chipscope was collected using an embedded processor design (eMIPS) which uses 18,268 slice registers and 21,237 slice LUTs of a Xilinx xc5vlx110t, at 26% and 30% utilization respectively. The area overhead for scan-chain based solutions also varies with design and can go up to 100% [1,2,6]. In terms of preparation time, Chipscope must go through the implementation phase which includes translation, mapping, PAR, and through the bitstream generation phase every time a setting is changed.…”

“…The former inserts additional circuit elements, either by hand or by some tool, to implement a scan-chain inside the user design [1,2,6]. Although this facilitates viewing the entire state of the circuit, the area penalty and change in timing behavior is significant.…”