Power-efficient FSM mapping in FPGAs through SEMB dormancy control

Janarthanan, A.D.; Tiwari, Anurag; Tomko, Karen

doi:10.1109/mwscas.2007.4488635

Cited by 4 publications

(2 citation statements)

References 5 publications

(6 reference statements)

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“…Researchers have devoted significant attention to the optimization of Finite State Machine (FSM) implementations regarding area, speed, or power consumption over decades [1][2][3][4][5][6][7][8]. Current Field Programmable Gate Array (FPGA) devices include Embedded Memory Blocks (EMBs), which allow, among other elements, the implementation of ROM memory.…”

Section: Introductionmentioning

confidence: 99%

A New Approach for Implementing Finite State Machines with Input Multiplexing

Garcia-Vargas,

Senhadji-Navarro

2023

Electronics

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The model called Finite State Machine with Input Multiplexing (FSMIM) was proposed as a mechanism for implementing Finite State Machines (FSMs) using ROM memory. This paper presents a novel approach for achieving more efficient FSMIM implementations in Field Programmable Gate Array (FPGA) devices. The aim of the proposed approach is to obtain further reductions in the use of Embedded Memory Blocks (EMBs). Unlike previous works, the proposed approach reduces the depth of the ROM by grouping states before simplifying the input selectors of the FSMIM. For this purpose, a new strategy for grouping states is proposed, and its optimality is proven. In addition, a new variant of the Minimum Maximal k-Partial Matching (MMKPM) problem and its corresponding Integer Linear Programming (ILP) formulation are proposed for simplifying input selectors. The proposed approach requires a significantly smaller number of EMBs than the approaches proposed previously.

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Section: Introductionmentioning

confidence: 99%

A New Approach for Implementing Finite State Machines with Input Multiplexing

Garcia-Vargas,

Senhadji-Navarro

2023

Electronics

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“…In digital design, the implementation of Finite State Machines (FSMs) has received attention from researchers for decades [1][2][3][4][5][6][7][8]. Optimizing FSM implementations in terms of area, speed or power consumption is essential to meet the design constraints demanded by applications.…”

Section: Introductionmentioning

confidence: 99%

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

García-Vargas

Senhadji-Navarro

2022

Des Autom Embed Syst

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Finite State Machines with Input Multiplexing (FSMIMs) were proposed in previous work as a technique for efficient mapping Finite State Machines (FSMs) into ROM memory. In this paper, we present new contributions to the optimization process involved in the implementation of FSMIMs in Field Programmable Gate Array (FPGA) devices. This process consists of two stages: (1) the simplification of the bank of input selectors of the FSMIM, and (2) the reduction of the depth of the ROM. This has a significant impact both on the number of used Look-Up Tables (LUTs) and on the number of the Embedded Memory Blocks (EMBs) required by the ROM. For the first stage, we present two approaches to optimize FSMIM implementations based on the Minimum Maximal k-Partial Matching (MMKPM) problem: one of them applies the greedy algorithm for the MMKPM problem, and the other based on a new multiobjetive variant of the MMKPM and its corresponding Integer Linear Programing formulation. We also propose a modification of the second stage, in which the characteristics of EMBs are taken into account to improve implementation results. The new optimization process significantly reduces the number of used FPGA resources with respect to the previous one. In addition, the proposed approaches achieve an adequate trade-off between the usage of EMBs and LUTs with respect to conventional FSM implementations based on ROM and to those based on LUT.

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Performance evaluation of RAM-based implementation of Finite State Machines in FPGAs

Senhadji-Navarro

García-Vargas

Guisado

2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the particular features of different FPGA families, like the size of LUTs, the size of memory blocks, the number of embedded multiplexer levels and the specific decoding logic for distributed RAM. Our study can be useful for efficiently implementing FPGA-based state machines.

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Power-efficient FSM mapping in FPGAs through SEMB dormancy control

Cited by 4 publications

References 5 publications

A New Approach for Implementing Finite State Machines with Input Multiplexing

A New Approach for Implementing Finite State Machines with Input Multiplexing

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

Performance evaluation of RAM-based implementation of Finite State Machines in FPGAs

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