We report a systematic study of the relationship between crystal quality and electrical properties of InAs nanowires grown by MOVPE and MBE, with crystal structure varying from wurtzite to zinc blende. We find that mixtures of these phases can exhibit up to 2 orders of magnitude higher resistivity than single-phase nanowires, with a temperature-activated transport mechanism. However, it is also found that defects in the form of stacking faults and twin planes do not significantly affect the resistivity. These findings are important for nanowire-based devices, where uncontrolled formation of particular polytype mixtures may lead to unacceptable device variability.

Group III−V nanowires offer the exciting possibility of epitaxial growth on a wide variety of substrates, most importantly silicon. To ensure compatibility with Si technology, catalyst-free growth schemes are of particular relevance, to avoid impurities from the catalysts. While this type of growth is well-documented and some aspects are described, no detailed understanding of the nucleation and the growth mechanism has been developed. By combining a series of growth experiments using metal−organic vapor phase epitaxy, as well as detailed in situ surface imaging and spectroscopy, we gain deeper insight into nucleation and growth of self-seeded III−V nanowires. By this mechanism most work available in literature concerning this field can be described.

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Sweden 6 *These authors contributed equally 7 III−V semiconductors have attractive transport properties suitable for low-power, high-speed 8 complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to 9 co-integration of III−V n-and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on 10 low-cost Si substrates have so far hindered their use for large scale logic circuits. Using a novel 11 approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one 12 single growth step, we here demonstrate n-and p-type, III−V MOSFETs monolithically integrated on a 13Si substrate with high Ion/Ioff ratios using a dual channel, single gate-stack design processed 14 simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic 15 gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale 16 III−V MOSFET circuits on Si. 17 Keywords: III−V, CMOS, nanowire, inverter, NAND, InAs, GaSb, low-power logic, Si 18Geometric scaling has for decades been the main technology drive for integrated Si circuits whereas 19 materials integration plays an important role in the continued technology evolution. In future 20 generations, III−V semiconductors are considered candidates to replace Si as channel material in 21MOSFETs due to their high mobilities and injection velocities that will enable voltage scaling to 22 reduce the power consumption at maintained performance The vertical device geometry is attractive, since it allows for aggressive gate length scaling due to the 41 superior electrostatics of the gate-all-around geometry and a small device footprint enabling high 42 density circuits. In addition, Yakimets et al. have predicted power savings of 10-15% for a vertical 43 device layout as compared to a lateral geometry for the 7 nm technology node 20 . In this work we 44 have focused on InAs and GaSb as the channel materials based on their respective high electron and 45 hole mobilities suitable to achieve high performance of both n-and p-type MOSFETs 1 and 46 demonstrate the growth of both materials on Si substrates by metal-organic vapor phase epitaxy 47 (MOVPE) in a single growth step. The growth step reduces the need for complex processing 48 simplifying fabrication saving cost and time. Both n-and p-type MOSFETs exhibit high Ion/Ioff ratios 49 using the same gate stack, which is known to be a critical concern for III−V MOSFETs. which are substantial benefits as compared to growth approaches directly on Si 17, 22 . To achieve 56 selective growth of both types of nanowires, we exploit the fact that the chemical potential of 57 material dissolved in an Au particle during growth is increased with decreasing particle size due to 58 the higher surface-to-volume ratio. Eventually, the chemical potential approaches that of the gas 59 phase, reducing the driving force for material transport to the particles what is known as the Gibbs-60Thompson effect 23 . Since the solubil...

We present electrical characterization of GaSb/InAs(Sb) nanowire tunnel field-effect transistors. The broken band alignment of the GaSb/InAs(Sb) heterostructure is exploited to allow for inter-band tunneling without a barrier, leading to high on-current levels. We report a maximum drive current of 310 µA/µm at VDS = 0.5 V. Devices with scaled gate oxides display transconductances up to gm = 250 mS/mm at VDS = 300 mV, normalized to the nanowire circumference at the axial heterojunction.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.