Vertical InAs Nanowire Wrap Gate Transistors with f_t > 7 GHz and f_max > 20 GHz

Abstract

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Hybrid Nanowire Ion-to-Electron Transducers for Integrated Bioelectronic Circuitry

“…[26,27] While the hysteresis is a feature of the quasi-dc characteristics, it has a lesser influence on the ac characteristics providing device operation is sufficiently fast that surface state trap occupancy remains quasistatic. One example is the GHz operation of InAs nanowire transistors [28] even when the quasi-dc characteristics exhibit hysteresis. [29] We now turn to data showing that surface states do not impede high fidelity transduction of biological/ionic signals.…”

RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates

“…The source-gate spacer was achieved by spinning a S1800 series photoresist and ashing it to a thickness of about 150 nm. The wrap-gate metal of 60 nm W (planar thickness) was deposited by DC sputtering and etched back to a gate length of about 250 nm assisted by a thinned down photoresist and reactive ion etching (RIE) in a SF 6 and Ar gas mixture. The gate-drain spacer was applied in the same way as the sourcegate spacer and was then used as an etch mask for removing the gate oxide from the upper part of the nanowires in a BOE wet etch.…”

“…Earlier studies on an RF-compatible process on semi-insulating (S.I.) InP substrates have yielded a unity current-gain cut-off frequency, f t = 7.5 GHz and a maximum oscillation frequency, f max = 22 GHz, mainly limited by the parasitic capacitances in the vertical geometry [6]. InAs transistors have also previously been fabricated successfully from InAs nanowires directly grown on Si substrates.…”

Low-Frequency Noise in Vertical InAs Nanowire FETs

“…Good DC performance of vertical InAs NW transistors based on arrays of nanowires with 50 nm gate length has been demonstrated [2], with g m = 0.5 S/mm and a subthreshold slope of 90 mV/decade. We have recently also investigated the radio frequency (RF) performance of similar InAs nanowire FETs [3]. Here we present data of the DC and 1/f characteristic for FETs based on individual vertical InAs NWs.…”