The thermal and gate-voltage dependencies for the capture and emission times of random telegraph signals have been theoretically analyzed in a Si-SiO 2 interface. A quasi-two-dimensional treatment of the interaction between a neutral near-interface oxide trap and an electron in the subband of the inversion layer has been developed to obtain expressions for the capture and emission times where the influence of the trap parameters ͑energy depth, distance to the interface, and electron-phonon coupling factor͒ is clearly shown. This analysis combines multiphonon-emission theory, tunnel transition probability and the electrostatic Coulomb barrier effect, allowing us to reproduce experimental data for traps in different devices, temperatures, and bias conditions. As a result, trap distances to the interface, trap energy levels, and electron-phonon couplings have been calculated. The character of single electron transitions in this process let us show that the ground and first excited subbands, with similar capture and emission times, are the most important contributors to the phenomenon. ͓S0163-1829͑97͒07039-2͔

We demonstrate the confinement of acoustic phonons in ultrathin silicon layers and study its effect on electron mobility. We develop a model for confined acoustic phonons in an ideal single-layer structure and in a more realistic three-layer structure. Phonon quantization is recovered, and the dispersion relations for distinct phonon modes are computed. This allows us to obtain the confined phonon scattering rates and, using Monte Carlo simulations, to compute the electron mobility in ultrathin silicon on insulator inversion layers. Thus, comparing the results with those obtained using the bulk phonon model, we are able to conclude that it is very important to include confined acoustic phonon models in the electron transport simulations of ultrathin devices, if we want to reproduce the actual behavior of electron transport in silicon layers of nanometric thickness.

Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO2)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO2 adjacent to the Schottky junction of G/Si. A certain threshold voltage (VT) is required before this can be observed, and its origins are similar to that of the threshold voltage in metal oxide semiconductor field effect transistors. A physical model serves to explain the large photocurrents underneath SiO2 by the formation of an inversion layer in Si. Our findings contribute to a basic understanding of graphene/semiconductor hybrid devices which, in turn, can help in designing efficient optoelectronic devices and systems based on such 2D/3D heterojunctions.

Finding an inexpensive and scalable method for the mass production of memristors will be one of the key aspects for their implementation in end-user computing applications. Herein, we report pioneering research on the fabrication of laser-lithographed graphene oxide memristors. The devices have been surface-fabricated through a graphene oxide coating on a polyethylene terephthalate substrate followed by a localized laser-assisted photo-thermal partial reduction. When the laser fluence is appropriately tuned during the fabrication process, the devices present a characteristic pinched closed-loop in the current-voltage relation revealing the unique fingerprint of the memristive hysteresis. Combined structural and electrical experiments have been conducted to characterize the raw material and the devices that aim to establish a path for optimization. Electrical measurements have demonstrated a clear distinction between the resistive states, as well as stable memory performance, indicating the potential of laser-fabricated graphene oxide memristors in resistive switching applications.

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