Relaxation-free characterization of Flash programming dynamics along P-E cycling

Abstract

A novel Flash endurance characterization approach is presented, allowing delay-free READ operations and thus a realistic electrostatic description at each cycle before any device relaxation. Systematic measurement of time-dependent drain current during Hot Carrier programming is shown to provide an extended description of Flash programming dynamics with a 5ns time resolution, including tunnel oxide transport.

Hot Carrier Stress modeling: From degradation kinetics to trap distribution evolution

“…A reasonable explanation of this slight disagreement relies on the presence of trapped electrons in the oxide. Indeed, their influence for this technology has been demonstrated to be significant [18], and a fast measurement setup would be required [19]. However, as already highlighted in Section II, for such long stress time, under nominal P/E biases, the Flash cell can be considered "failed", since the programming window is lower than the threshold dispersion.…”

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

“…Thus, we show the importance to consider the dynamic source current during a Channel Hot Electron (CHE) operation, to find the real cell coupling factor. In this way it is possible to extract the real floating gate potential (VFG) variation during the programming time (tP), as qualitatively proposed in [19]. Moreover, in the second section, a smart test algorithm is presented to induce a quantitative degradation on the equivalent transistor corresponding to the memory cell during cycling.…”