Process integration and testing of TSV Si interposers for 3D integration applications

Abstract

Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules.The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6" wafers. The front-side MLM was comprised of 4 metal routing layers (2 µm Cu with 2 µm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 mΩ per via. TSV dimensions of 100 and 80 µm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 mΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm x 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), waferlevel packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6" wafers. Via dimensions for the viasfirst interposers were 50 µm diameter x 315 µm depth or 80 µm diameter x 315 µm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 µm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

Demonstration of low cost TSV fabrication in thick silicon wafers

“…Compared to wire-bond interconnections, TSVs offer the potential for higher density input/output (I/O) configurations as well as a significant reduction of the size and weight of the package [3][4][5][6]. The combination of both can translate into more functionality and a smaller overall form factor.…”