The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.
In 2019 SWIR Vision Systems introduced its 2.1 MP Acuros cameras to the industrial imaging market, becoming the first company globally to commercialize high resolution, quantum‐dot based image sensors. Since this product introduction, SWIR Vision Systems has continued to advance the performance of its colloidal quantum dot detector architecture. These advances include demonstrating detectors with 940 nm QE's > 50% and extended wavelength eSWIR detectors with spectral response from 350 nm to 2100 nm. This paper will provide an overview of our approach to fabricating focal plane arrays, will describe recent results fabricating Vis‐SWIR and eSWIR CQD® detector arrays, and will show imaging demonstrations of these sensors in a variety of applications.
An electrically functional freestanding Si interposer for 3-D heterogeneous integration applications is designed and successfully fabricated. The interposer employs multilevel metallization (MLM) on the frontside of the wafer and Cu-filled through-Si vias (TSVs) and MLM on the backside. The MLM structures use electroplated Cu and polymer dielectrics of the type used in wafer-level packaging. The fabrication flow of the 3-D interposer test vehicle incorporates the formation of TSVs, the deposition and patterning of two routing levels of frontside MLM, wafer thinning, and the deposition and patterning of backside MLM. TSVs 80 µm in diameter, 315 µm in depth, and 80 µm in diameter, 265-µm depth (4:1 or 3:1 aspect ratio, respectively) are demonstrated. The frontside and backside MLM were formed with 3-µm-thick Cu routing layers and 5-µm-thick spin-on dielectric layers. Daisy chains consisting of 528 TSVs connecting the frontside and backside metal layers are tested for electrical continuity. Individual TSV operability exceeds 99.98%. Details of the MLM and TSV process modules, including thermal stabilization of Cu-filled TSVs and process integration required to successfully obtain the high TSV operability, are described. Index Terms-Multilevel metallization (MLM), Si interposer, through-Si vias (TSVs).
High-current electron field emitters are of interest for many applications, but state-of-the-art devices suffer from limitations such as high turn-on macroscopic field, low macroscopic current density, poor emission stability, and short lifetime. Field emitter arrays with a high spatial density of uniform emitters have the potential to address these problems. This work presents the process development, fabrication, and testing of a novel field emitter array. The authors employed electron beam lithography and templated electrodeposition to fabricate a high spatial density array of metallic nanowires, resulting in electron emission with high macroscopic current density (2 A/cm2) and low turn-on macroscopic field (4.35 V/μm). Templated electrodeposition of metallic nanowire arrays is a promising method for producing high performance field emitters.
Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules.The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6" wafers. The front-side MLM was comprised of 4 metal routing layers (2 µm Cu with 2 µm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 mΩ per via. TSV dimensions of 100 and 80 µm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 mΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm x 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), waferlevel packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6" wafers. Via dimensions for the viasfirst interposers were 50 µm diameter x 315 µm depth or 80 µm diameter x 315 µm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 µm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.
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