The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

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In 2019 SWIR Vision Systems introduced its 2.1 MP Acuros cameras to the industrial imaging market, becoming the first company globally to commercialize high resolution, quantum‐dot based image sensors. Since this product introduction, SWIR Vision Systems has continued to advance the performance of its colloidal quantum dot detector architecture. These advances include demonstrating detectors with 940 nm QE's > 50% and extended wavelength eSWIR detectors with spectral response from 350 nm to 2100 nm. This paper will provide an overview of our approach to fabricating focal plane arrays, will describe recent results fabricating Vis‐SWIR and eSWIR CQD® detector arrays, and will show imaging demonstrations of these sensors in a variety of applications.

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An electrically functional freestanding Si interposer for 3-D heterogeneous integration applications is designed and successfully fabricated. The interposer employs multilevel metallization (MLM) on the frontside of the wafer and Cu-filled through-Si vias (TSVs) and MLM on the backside. The MLM structures use electroplated Cu and polymer dielectrics of the type used in wafer-level packaging. The fabrication flow of the 3-D interposer test vehicle incorporates the formation of TSVs, the deposition and patterning of two routing levels of frontside MLM, wafer thinning, and the deposition and patterning of backside MLM. TSVs 80 µm in diameter, 315 µm in depth, and 80 µm in diameter, 265-µm depth (4:1 or 3:1 aspect ratio, respectively) are demonstrated. The frontside and backside MLM were formed with 3-µm-thick Cu routing layers and 5-µm-thick spin-on dielectric layers. Daisy chains consisting of 528 TSVs connecting the frontside and backside metal layers are tested for electrical continuity. Individual TSV operability exceeds 99.98%. Details of the MLM and TSV process modules, including thermal stabilization of Cu-filled TSVs and process integration required to successfully obtain the high TSV operability, are described. Index Terms-Multilevel metallization (MLM), Si interposer, through-Si vias (TSVs).