Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Lannon, John; Hilton, Allan; Huffman, Alan; Butler, Marianne; Malta, Dean; Gregory, Chris; Temple, Dorota

doi:10.1109/tcpmt.2013.2284580

Cited by 10 publications

(5 citation statements)

References 12 publications

(18 reference statements)

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“…Through Silicon Vias have been demonstrated by RTI [5] for use with other technologies, but had not been thoroughly demonstrated with thicker wafers and with Quilt Packaging processes. To take the next step in the development of a quilted large format array, a test vehicle was fabricated using both TSVs and QP.…”

Section: Through Silicon Vias Chains As Test Vehiclementioning

confidence: 99%

Scalable emitter array development for infrared scene projector systems

et al. 2014

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Several new technologies have been developed over recent years that make a fundamental change in the scene projection for infrared hardware in the loop test. Namely many of the innovations are in Read In Integrated Circuit (RIIC) architecture, which can lead to an operational and cost effective solution for producing large emitter arrays based on the assembly of smaller sub-arrays. Array sizes of 2048x2048 and larger are required to meet the high fidelity test needs of today's modern infrared sensors. The Test Resource Management Center (TRMC) Test and Evaluation/Science & Technology (T&E/S&T) Program through the U.S. Army Program Executive Office for Simulation, Training and Instrumentations (PEO STRI) has contracted with SBIR and its partners to investigate integrating new technologies in order to achieve array sizes much larger than are available today. SBIR and its partners have undertaken several proof-of-concept experiments that provide the groundwork for producing a tiled emitter array. Herein we will report on the results of these experiments, including the demonstration of edge connections formed between different ICs with a gap of less than 10µm.

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Section: Through Silicon Vias Chains As Test Vehiclementioning

confidence: 99%

Scalable emitter array development for infrared scene projector systems

et al. 2014

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“…4 and 5(b). Following the TSV process is usually the multilevel metallization, and some works and methods [12], [13] have been reported. For the open-structure TSVs, spray coating or dry film is used for the patterning of the metal layer.…”

Section: Application For 3-d Hetero-integrationmentioning

confidence: 99%

Investigation of Wet-Etching- and Multiinterconnection-Based TSV and Application in 3-D Hetero-Integration

Chen

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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Through-silicon-via (TSV) fabrication using deep reactive-ion etching has many constraints, such as complicated process and high cost. This paper presents a novel fabrication method of TSVs based on double-sided anisotropic wet etching of (100)-oriented silicon wafer. To increase the I/O interconnection density, a metallization process of TSVs with multiinterconnection is first proposed and realized by spray coating and semiadditive plating process. Both TSVs with one wire and four wires are designed and fabricated. The open/short test validates the feasibility of the process, and the electrical resistances are about 1.2 and 0.2 , respectively. The proposed TSV with multiinterconnection is applied to the interposer fabrication, which is designed for the 3-D hetero-integration of GaAs photodetector and readout circuit, and demonstrates its application. This fabrication method is featured by both low cost and relatively high interconnection density. In addition, it has the advantages of simple process and reliable electrical interconnection, with potential applications to low or middle interconnection density cases.Index Terms-Multiinterconnection TSV, silicon interposer, wet etching.

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“…Further details of the interposer fabrication and testing are provided in other publications. [14,15] …”

Section: Tsv Processing and Interposer Fabricationmentioning

confidence: 99%

Characterization and modeling of copper TSVs for silicon interposers

Malta

Gregory

Lueck

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Silicon interposers enable advanced package architectures through the integration of multiple die and passive components onto a single silicon substrate, while offering high interconnect density and low thermal expansion mismatch. This paper will describe the processing and characterization of copper-filled through silicon vias (TSVs) for Si interposers and related three-dimensional wafer-level packaging (3D-WLP) applications. To evaluate potential reliability concerns, the thermomechanical behavior of Cu-filled TSVs was characterized experimentally over a range of TSV dimensions and also modeled using finite element analysis. The paper will include discussion of the correlation between the experimental observations and modeling data obtained for the TSV structures. Demonstrations of functional Si interposer substrates are also reported, based on three different design variations of TSV diameter and substrate thickness, respectively: 25 × 100m, 50 × 200m, and 80 × 300m. Finally, alternative TSV structures, based on Cu-lined vias with polymer filled cores, are demonstrated as a possible approach to reducing the thermomechanical concerns for Cu-filled TSVs in Si interposer or 3D-WLP substrates

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Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Cited by 10 publications

References 12 publications

Scalable emitter array development for infrared scene projector systems

Scalable emitter array development for infrared scene projector systems

Investigation of Wet-Etching- and Multiinterconnection-Based TSV and Application in 3-D Hetero-Integration

Characterization and modeling of copper TSVs for silicon interposers

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