Investigation of Wet-Etching- and Multiinterconnection-Based TSV and Application in 3-D Hetero-Integration

Abstract

Through-silicon-via (TSV) fabrication using deep reactive-ion etching has many constraints, such as complicated process and high cost. This paper presents a novel fabrication method of TSVs based on double-sided anisotropic wet etching of (100)-oriented silicon wafer. To increase the I/O interconnection density, a metallization process of TSVs with multiinterconnection is first proposed and realized by spray coating and semiadditive plating process. Both TSVs with one wire and four wires are designed and fabricated. The open/short test validates the feasibility of the process, and the electrical resistances are about 1.2 and 0.2 , respectively. The proposed TSV with multiinterconnection is applied to the interposer fabrication, which is designed for the 3-D hetero-integration of GaAs photodetector and readout circuit, and demonstrates its application. This fabrication method is featured by both low cost and relatively high interconnection density. In addition, it has the advantages of simple process and reliable electrical interconnection, with potential applications to low or middle interconnection density cases.Index Terms-Multiinterconnection TSV, silicon interposer, wet etching.