We describe a new method for removing thin, large area sheets of diamond from bulk or homoepitaxial diamond crystals. This method consists of an ion implantation step, followed by a selective etching procedure. High energy (4–5 MeV) implantation of carbon or oxygen ions creates a well-defined layer of damaged diamond that is buried at a controlled depth below the surface. For C implantations, this layer is graphitized by annealing in vacuum, and then etched in either an acid solution, or by heating at 550–600 °C in oxygen. This process successfully lifts off the diamond plate above the graphite layer. For O implantations of a suitable dose (3×1017 cm−2 or greater), the liftoff is achieved by annealing in vacuum or flowing oxygen. In this case, the O required for etching of the graphitic layer is also supplied internally by the implantation. This liftoff method, combined with well-established homoepitaxial growth processes, has considerable potential for the fabrication of large area single crystalline diamond sheets.

The electrical transport properties of simultaneously deposited, B-doped homoepitaxial and polycrystalline diamond thin films have been evaluated by Hall-effect and resistivity measurements over a temperature range of 80–600 K. The same films were later characterized by scanning electron microscopy, secondary-ion-mass spectroscopy, and an oxidation defect etch. The study involved four sets of chemical-vapor-deposited diamond films with individual B concentrations ranging from 1.5×1017 to 1.5×1020 cm−3. In each of the four cases the mobility of the polycrystalline film was lower than that of the homoepitaxial film by 1–2 orders of magnitude over the entire temperature range. Polycrystalline films also incorporated 2–4 times more B, had 3–5 times higher compensation ratios, and displayed activation energies that were 0.05–0.09 eV lower than in the homoepitaxial films. Hopping conduction was observed in both types of films at low temperatures, but was enhanced in polycrystalline films as evident by higher transition temperatures. Preliminary efforts have been made to evaluate these results by considering the possible effects of crystal structure, compensation, impurity segregation, grain-boundary trapping, and impurity conduction.

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

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The next generation of wireless infrastructure will rely heavily upon wide band gap semiconductors owing to their unique materials properties, including: their large bandgap, high thermal conductivity, and high breakdown field. To facilitate implementation of this next generation, a significant effort is required to make SiC MESFET and GaN HEMT microwave devices more suitable for widespread application. Currently, the interest in high-purity semiinsulating (HPSI) 4H-SiC is critically tied to its influence on microwave devices, whether performance or affordability. To address these issues, we have developed high-purity 3-inch and 100 mm 4H-SiC substrates with low micropipe densities (as low as 1.4 cm -2 in 3-inch and <60 cm -2 in 100 mm) and uniform semi-insulating properties (>10 9 Ωcm) over the full wafer diameter. These wafers possess typical residual shallow level contamination less than 1x10 16 cm -3 (5x10 15 nitrogen and 3x10 15 boron) with best nitrogen values of 3x10 14 . In this paper, we will report on the development of our HPSI growth process focusing on the specific areas of the assessment of semiinsulating character and device applicability.