Large quantities of microscopic red, green, and blue light-emitting diodes (LEDs) made of crystalline inorganic semiconductor materials micro-transfer printed in large quantities onto rigid or flexible substrates form monochrome and color displays having a wide range of sizes and interesting properties. Transfer-printed micro-LED displays promise excellent environmental robustness, brightness, spatial resolution, and efficiency. Passive-matrix and active-matrix inorganic LED displays were constructed, operated, and their attributes measured. Tests demonstrate that inorganic micro-LED displays have outstanding color, viewing angle, and transparency. Yield improvement techniques include redundancy, physical repair, and electronic correction. Micro-transfer printing enables revolutionary manufacturing strategies in which microscale LEDs are first assembled into miniaturized micro-system "light engines," and then micro-transfer printed and interconnected directly to metallized large-format panels. This paper reviews micro-transfer printing technology for micro-LED displays. FIGURE 3 -(A) Schematic illustration of a micro-transfer stamp that is rigid in horizontal directions and compliant in the vertical dimension. (B) Photograph of a stamp on a 225 × 225 mm glass back. (C) SEM of the stamp posts.FIGURE 4 -Photograph of a 50 × 50 mm stamp silicon master (A) and elastomer stamp (B). The stamp has an array of 250 by 250 posts on a 200-micron pitch with 62,500 posts. Journal of the SID 25/10, 2017 591 FIGURE 9 -Micrographs of an array of microscopic inorganic light-emitting diodes microtransfer printed to a metal-coated substrate (left) and emitting red light (right). The anodes are connected in common with a transparent aluminum zinc oxide anode.
A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.
No abstract
Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed "TSVs last", following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a "TSVs first" process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cufilled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.