Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

Abstract

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

Fabrication of TSV-based silicon interposers

“…As bottom clear etch time was increased, the TSV chains yield improved, but the isolation resistance decreased. This suggested that etching too long can result in loss of passivation at the via sidewalls and illustrates the need to carefully optimize the etch conditions for this key step [6]. For the full interposer wafers, electrical testing of the MLM layers showed up to 100% yield on 4-layer test chain structures which included 26,400 vias each.…”

“…The average measured contact resistance was 4mȍ for the dual damascene levels. [6] Thermal cycling of the TSV electrical test wafers showed no TSV via chain yield loss for up to three reflow cycles at 225ºC. A slight increase in 4-wire TSV resistance was observed, with a measured change of about 0.6 mȍ per reflow cycle [6].…”

“…Each could be applicable for making interposer wafers with the TSVs first approach. These are: 1) Cu / oxide MLM with CMP, as demonstrated in the vias-last interposers [6], and 2) Cu MLM with benzocyclobutene (BCB) spin-on dielectric and no CMP. The Cu-BCB process is more likely applicable for applications requiring fewer metal levels and lower metal pattern density.…”

“…The TSVs last, back-side unfilled vias process was used in the successful fabrication of TSV electrical test wafers, as well as full interposer wafers [6]. The electrical test wafers included TSV chains of up to 540 vias, in addition to 4-wire TSV resistance structures and TSV isolation structures, like those shown in Fig.…”

“…Currently, interposer technology is gaining significant momentum and will likely be one of the early 3D applications to move into commercial use. Silicon interposers with TSVs will provide a means of integrating multiple chips on a common package platform with smaller size, high I/O density, and reduced power [4][5][6]. There are a variety of advantages to using Si as the interposer substrate, mainly: 1) use of IC processing techniques for high density metallization, 2) established processes for deep Si etching of TSVs, and 3) CTE match between interposer substrate and bonded Si chips.…”