Hole Transport in Nanoscale p-type MOSFET SOI Devices with High Strain

Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

“…As Ge was being explored over the past few years, local Si straining techniques (using embedded SiGe and nitride stressor layers) were optimized to a degree that a four-fold increase in mobility over unstrained Si PFETs could be realized [6], [7]. Recently, Si PFETs with drain-currents reaching the 1-mA/µm level have been demonstrated by combining process-induced strain with (110) Si or high-κ/metal-gate stack [8], [9].…”

Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs

“…10, the simulated ballistic velocity enhancement relative to relaxed Si is provided for Si, biaxial compressive strained Si 0.45 Ge 0.55 pseudomorphic to relaxed Si, Ge, and biaxial compressive strained Ge pseudomorphic to relaxed Si 0.45 Ge 0.55 , all with added uniaxial strain. Simulations were performed by calculating the 2-D E−k dispersion relation using nextnano 3 . The simulated band structure was used as an input to FETtoy which calculates the ballistic current [26].…”

“…Starting at the 90-nm CMOS technology node, embedded SiGe source/drains (S/Ds) were used to introduce uniaxial compressive strain into the channel as a means to increase the p-MOSFET drive current [1]. The uniaxial strain imparted by the embedded SiGe S/D regions alters the intrinsic electrical properties of the channel, making it favorable for hole transport [2], [3]. The hole velocity in stateof-the-art strained-Si p-MOSFETs has been extracted, and a velocity enhancement is observed over comparable relaxed-Si devices [4].…”

“…Simulated ballistic velocity enhancement relative to relaxed Si with applied compressive uniaxial stress for Si, biaxial compressive strained Si 0.45 Ge 0.55 pseudomorphic to relaxed Si (Si 0.45 Ge 0.55 /Si), Ge, and biaxial compressive strained Ge pseudomorphic to relaxed Si 0.6 Ge 0.4 (Ge/Si 0.6 Ge 0.4 ). Simulations were performed using nextnano3 and FETtoy [24],[26].…”