Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

Bedell, Stephen W.; Majumdar, Amlan; Ott, J. A.; Arnold, John; Fogel, K.; Koester, Steven J.; Sadana, D. K.

doi:10.1109/led.2008.2000713

Cited by 56 publications

(38 citation statements)

References 10 publications

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“…31 This potential has indeed been demonstrated for pMOSFETs fabricated in biaxially compressively s-Ge epi layers. 32,33 In an attempt to exploit this for short-channel devices, processing has been performed on s-Ge substrates, which are schematically represented in Fig. 4a.…”

Section: Thin Strained Epitaxial Ge Layersmentioning

confidence: 99%

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

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Extended-defect aspects of state-of-the-art Ge-on-Si materials and devices are discussed with an emphasis on the impact of postgrowth thermal budget on the structural and electrical epilayer characteristics. The observations on the annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations ͑TDs͒. For the present processing conditions, the leakage current of Ge complementary metal oxide semiconductor compatible p + n junctions becomes independent of the TD density at about 10 7 cm −2 . © 2009 The Electrochemical Society. ͓DOI: 10.1149/1.3267514͔ All rights reserved. Defect engineering is a common practice in silicon-based integrated circuit and solar cell technology and has been extensively investigated during the past 2 decades, leading to its successful implementation in manufacturing lines. In addition, for sub-45 nm technologies, strain engineering is required to boost the device performance in agreement with the International Technology Roadmap for Semiconductors. In recent years, strong research efforts have also been focusing on the use of Ge-based channels for the sub-22 nm complementary metal oxide semiconductor ͑CMOS͒ node, 1 whereby epitaxial Ge-on-Si has a very strong potential. This also opens the door to achieve a full monolithic integration of Ge and III-V materials on a silicon substrate, leading to system-on-chip applications. The main challenge of the epitaxial deposition of Ge on Si is the 4% lattice mismatch and the difference in thermal expansion coefficient, which readily leads to the buildup of mechanical stress and, subsequently, its relaxation by the generation of misfit and threading dislocations ͑TDs͒.2,3 Therefore, the control of misfit and TDs during both substrate preparation and device processing is a must to arrive at a good-yielding, high performing technology. The aim of this paper is to summarize our recent developments in Geon-Si materials and devices and to address the remaining challenges. An extensive overview of the foregoing work can be found in Chap. 4 of Ref. 4.The focus in this work is on the defect formation and control during the fabrication of Ge virtual substrates on silicon by chemical vapor deposition. Hereby, several approaches can be followed 2-4 to optimize the threading dislocation density ͑TDD͒ either by the use of a relaxed SiGe-graded buffer layer or by the direct deposition of a thick Ge epitaxial layer on silicon. Three different cases are considered, whereby the impact of a postgrowth ͑PG͒ anneal on the TDD is highlighted, and the impact on the electrical device performance is mainly evaluated through the leakage current of p + n junctions fabricated in these layers. The procedures to separate the area from the perimeter leakage current have been outlined previously. 5,6 It is demonstrated that a PG anneal or thermal budget may have both beneficial and detrimental effects, depending on the application and type of layer. For a relaxed virtual Ge substrate, the PG anneali...

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Section: Thin Strained Epitaxial Ge Layersmentioning

confidence: 99%

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

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“…Refs. [15][16][17][18][19][20][21][22]. The valence band offset determines the threshold voltage and gate-to-channel capacitance of such devices.…”

Section: Introductionmentioning

confidence: 99%

Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates

et al. 2012

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MOS-capacitors were fabricated on type II staggered gap strained-Si/strained-Ge heterostructures epitaxially grown on relaxed SiGe substrates of various Ge fractions. Quasistatic quantum mechanical capacitance-voltage (CV) simulations were fit to experimental CV measurements to extract the band alignment of the strained layers. The valence band offset of the strained-Si/strained-Ge heterostructure was found to be 770, 760, and 670 meV for 35, 42, and 52% Ge in the relaxed SiGe substrate, respectively. These values are approximately 100 meV larger than expected on the basis of the usually recommended band offsets for modeling Si/Ge structures. It is shown that the larger valence band offsets found here are consistent with an 800 meV average valence band offset between Si and Ge, which also explains the type II band alignment observed in strained-Si 1-x Ge x on unstrained-Si heterostructures.

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“…However, its higher permittivity makes it very susceptible to short channel effects (SCEs). To improve the subthreshold characteristics, ultrathin-body (UTB) germanium-on-insulator (GeOI) MOSFET has been proposed as a promising device architecture [7]- [10] and shows better control of SCEs than the bulk germanium MOSFET. Silicon-on-nothing [SON, buried insulator (BI) permittivity = 1] MOSFETs are also widely discussed as a possible alternative due to its reduced source-to-drain coupling through the BI [11]- [15].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET

2011

IEEE Trans. Nanotechnology

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This paper examines the electrostatic integrity of ultrathin-body (UTB) germanium-on-nothing (GeON) MOSFET using theoretically calculated subthreshold swing from the analytical solution of Poisson's equation. Our results indicate that UTB GeON MOSFETs with the ratio of channel length (L g ) to channel thickness (T ch ) around 4 can show comparable subthreshold swing to that of the silicon-on-nothing counterparts. The impact of buried insulator (BI) thickness (T B I ) and BI permittivity on the electrostatic integrity of the UTB germanium channel devices are also examined.

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Mobility Scaling in Short-Channel Length Strained Ge-on-Insulator P-MOSFETs

Cited by 56 publications

References 10 publications

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Extraction of large valence-band energy offsets and comparison to theoretical values for strained-Si/strained-Ge type-II heterostructures on relaxed SiGe substrates

Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET

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