Atomically thin molybdenum disulfide (MoS) is an ideal semiconductor material for field-effect transistors (FETs) with sub-10 nm channel lengths. The high effective mass and large bandgap of MoS minimize direct source-drain tunneling, while its atomically thin body maximizes the gate modulation efficiency in ultrashort-channel transistors. However, no experimental study to date has approached the sub-10 nm scale due to the multiple challenges related to nanofabrication at this length scale and the high contact resistance traditionally observed in MoS transistors. Here, using the semiconducting-to-metallic phase transition of MoS, we demonstrate sub-10 nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS. This is done in a 7.5 nm half-pitch periodic chain of transistors where semiconducting (2H) MoS channel regions are seamlessly connected to metallic-phase (1T') MoS access and contact regions. The resulting 7.5 nm channel-length MoS FET has a low off-current of 10 pA/μm, an on/off current ratio of >10, and a subthreshold swing of 120 mV/dec. The experimental results presented in this work, combined with device transport modeling, reveal the remarkable potential of 2D MoS for future sub-10 nm technology nodes.

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Strained Si n -channel metal-oxide-semiconductor field-effect transistors formed on very thin SiGe relaxed layer fabricated by ion implantation technique Appl. Phys. Lett. 90, 202101 (2007); 10.1063/1.2739324 Asymmetric strain relaxation in patterned SiGe layers: A means to enhance carrier mobilities in Si cap layers Appl. Phys. Lett. 90, 032108 (2007); 10.1063/1.2431702High-quality strain-relaxed SiGe alloy grown on implanted silicon-on-insulator substrate Surface channel strained Si metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ are a leading contender for future high performance complementary metal-oxide-semiconductor ͑CMOS͒ applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n-and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n-and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFETs. Loss of carrier confinement severely limits the mobility of devices with the thinnest channels. Overall, surface channel strained Si MOSFETs are found to exhibit large carrier mobility enhancements over coprocessed bulk Si devices. This, combined with the high process stability exhibited by these devices, makes them superb candidates for future CMOS applications.

A simple semiempirical model I D (V GS , V DS ) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called "top-ofthe-barrier-transport" model, and we refer to it as the "virtual source" (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage V GS = V dd ); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically I off at V GS = 0 V) and at high V DS ; 5) total resistance at V DS = 0 V and V GS = V dd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.

We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.

By use of x-ray lithography Si inversion layers have been fabricated with width ~25 nm and mobility -15000 cm 2 /V s. These display oscillations in their conductance that are periodic in the number of electrons per unit length, even in zero magnetic field. The oscillations reflect an oscillatory activation energy of the conductance and are accompanied by unusual nonlinearities suggestive of pinned chargedensity waves.PACS numbers: 73.20.Dx, 71.45.Lr, 72.15.Ni A variety of novel lithographic techniques have been used 1 " 4 to create quasi-one-dimensional inversion layers in Si metal-oxide-semiconductor field-effect transistors (MOSFET's), in order to study how their conductance depends on carrier density. It is remarkable that, despite the differences in the structure of the devices, the results are qualitatively similar: one observes random, but time-independent, fluctuations in the conductance G as a function of electron density, which are exponentially large at small G and of order e 2 /h at large G. The latter are the universal conductance fluctuations, 4,5 seen in quasi-one-dimensional metals as well, 6 and the former result from one-dimensional variable-range hopping. 1,7 Among the inversion layers studied to date, those with smaller width w generally 4 had lower mobility (,u~3000 cm 2 /V s is typical for w -40 nm). We report here studies of narrower inversion layers (w -25 nm) with higher ju (15 000 cm 2 /V s) that reveal qualitatively new behavior. The variations in G are still exponentially large at small electron density and very small at high density, but the variations are periodic in the density of electrons in the inversion layer, even in the absence of a magnetic field.The narrow inversion layers were created with a dual gate device (Fig. 1) with a 70-nm gap in the lower gate. The lower gate shields the Si/SiC>2 interface from the upper gate, so that when the lower gate is biased below threshold relative to the Si, the inversion layer is confined to the region beneath the gap. In fact, the fringing fields of the lower gate confine the electrons to a region substantially narrower than the gap, as discussed below. The gap in the lower gate was created with x-ray nanolithography and liftoff. 8 The lower gate was made of refractory metal in order that damage to the Si/SiC>2 interface caused by processing could be repaired by a hightemperature vacuum anneal. The mobility was 15 000 cm 2 /V s at 4.2 K for two-dimensional (2D) MOSFET's on the same wafer subjected to the same processing steps as the narrow devices. This corresponds to a mean free path of ~~100 nm. The lower gate extends over only part of the length of the upper gate, which overlaps source and drain n + pads; this means that contact to the narrow inversion channel is made by wide, 2D-electrongas regions. Although two leads are connected to each of these 2D regions, this is fundamentally a two-probe measurement of the narrow MOSFET. The detailed fabrication procedure is reported elsewhere. 8 Measurement were performed at temperatures of 100 m...

We report a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device. It is found that Ge diffusion depends on the amount of GeO2 formed at the HfO2∕Ge interface and can be retarded by surface nitridation. It is speculated that Ge diffusion is in the form of GeO or Ge-riched HfGeO. Effective suppression of Ge diffusion by NH3 nitridation has resulted in improved electrical properties of TaN∕HfO2∕Ge MOS device, including equivalent oxide thickness (EOT), leakage current, hysteresis, and interface state density. The degradation of leakage current after high temperature post metallization anneal (PMA) is found to be due to Ge diffusion.

Two-dimensional electronics based on single-layer (SL) MoS offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.